Dual metal gates using one metal to alter work function of another metal

Abstract

Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

1 . A set of dual metal gates comprising:
 a first gate including a first metal having a first work function;   a second gate including the first metal and a second metal, the second metal structured to alter the first work function to a second work function for the second gate; and   a gate dielectric layer under the first gate and the second gate, wherein only the first metal contacts the gate dielectric layer.   
     
     
         2 . The dual metal gates of  claim 1 , wherein one of the dual metal gates is for an n-type metal oxide semiconductor (NMOS) device and the other dual metal gate is for a p-type metal oxide semiconductor (PMOS). 
     
     
         3 . The dual metal gates of  claim 1 , wherein a combination of the first metal and the second metal, respectively, are selected from the group consisting of: titanium nitride (TiN) and tantalum carbon nitride (TaCN), hafnium silicide (HfSi) and titanium silicon nitride (TiSiN), tantalum (Ta) and ruthenium (Ru), tantalum carbon nitride (TaCN) and titanium nitride (TiN). 
     
     
         4 . The dual metal gates of  claim 1 , wherein the first metal includes one of: titanium nitride (TiN), hafnium silicide (HfSi), tantalum (Ta) and tantalum carbon nitride (TaCN), and the second metal includes one of: tantalum carbon nitride (TaCN), titanium nitride (TiN) and ruthenium (Ru). 
     
     
         5 . The dual metal gates of  claim 1 , wherein the gate dielectric layer includes one of: hafnium silicate (HfSiO x ), hafnium oxide (HfO 2 ), zirconium silicate (ZrSiO x ), zirconium oxide (ZrO 2 ) and silicon oxide (SiO 2 ). 
     
     
         6 . The dual metal gates of  claim 1 , wherein the first gate is for an n-type metal oxide semiconductor (NMOS) device. 
     
     
         7 . The dual metal gates of  claim 6 , wherein the second gate is for a p-type metal oxide semiconductor (PMOS) device. 
     
     
         8 . The dual metal gates of  claim 7 , wherein the NMOS device and the PMOS device are separated by a trench isolation region. 
     
     
         9 . The dual metal gates of  claim 1 , further comprising a silicon layer over the first gate and the second gate. 
     
     
         10 . The dual metal gates of  claim 9 , wherein the silicon layer directly contacts the first metal layer in the first gate, and the silicon layer is prevented from contacting the first metal layer in the second gate by the second metal layer. 
     
     
         11 . The dual metal gates of  claim 10 , wherein the silicon layer directly contacts the second metal layer in the second gate. 
     
     
         12 . A set of dual metal gates comprising:
 a first gate including a first metal having a first work function;   a second gate including the first metal and a second metal, the second metal structured to alter the first work function to a second work function for the second gate;   a gate dielectric layer under the first gate and the second gate, wherein only the first metal contacts the gate dielectric layer; and   a silicon layer over the first gate and the second gate, wherein the silicon layer directly contacts the first metal layer in the first gate, and the silicon layer is prevented from contacting the first metal layer in the second gate by the second metal layer.   
     
     
         13 . The dual metal gates of  claim 12 , wherein one of the dual metal gates is for an n-type metal oxide semiconductor (NMOS) device and the other dual metal gate is for a p-type metal oxide semiconductor (PMOS). 
     
     
         14 . The dual metal gates of  claim 12 , wherein a combination of the first metal and the second metal, respectively, are selected from the group consisting of: titanium nitride (TiN) and tantalum carbon nitride (TaCN), hafnium silicide (HfSi) and titanium silicon nitride (TiSiN), tantalum (Ta) and ruthenium (Ru), tantalum carbon nitride (TaCN) and titanium nitride (TiN). 
     
     
         15 . The dual metal gates of  claim 12 , wherein the first metal includes one of: titanium nitride (TiN), hafnium silicide (HfSi), tantalum (Ta) and tantalum carbon nitride (TaCN), and the second metal includes one of: tantalum carbon nitride (TaCN), titanium nitride (TiN) and ruthenium (Ru). 
     
     
         16 . The dual metal gates of  claim 12 , wherein the gate dielectric layer includes one of: hafnium silicate (HfSiO x ), hafnium oxide (HfO 2 ), zirconium silicate (ZrSiO x ), zirconium oxide (ZrO 2 ) and silicon oxide (SiO 2 ). 
     
     
         17 . The dual metal gates of  claim 12 , wherein the first gate is for an n-type metal oxide semiconductor (NMOS) device. 
     
     
         18 . The dual metal gates of  claim 17 , wherein the second gate is for a p-type metal oxide semiconductor (PMOS) device. 
     
     
         19 . The dual metal gates of  claim 18 , wherein the NMOS device and the PMOS device are separated by a trench isolation region. 
     
     
         20 . The dual metal gates of  claim 12 , wherein the silicon layer directly contacts the second metal layer in the second gate.