Semiconductor package

Abstract

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

1 . A semiconductor package, comprising:
 a semiconductor die; and   a first conductive bump and a second conductive bump respectively disposed on the semiconductor die, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.   
     
     
         2 . The semiconductor package as claimed in  claim 1 , wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the central area, and the second conductive bump is disposed on the semiconductor die in the peripheral area. 
     
     
         3 . The semiconductor package as claimed in  claim 1 , wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the peripheral area, and the second conductive bump is disposed on the semiconductor die in the central area. 
     
     
         4 . The semiconductor package as claimed in  claim 1 , wherein the first conductive bump and the second conductive bump are alternatively disposed on the semiconductor die. 
     
     
         5 . The semiconductor package as claimed in  claim 1 , wherein the first conductive bump and the second conductive bump are randomly disposed on the semiconductor die. 
     
     
         6 . The semiconductor package as claimed in  claim 1 , wherein the first conductive bump is a circular shape from the top view. 
     
     
         7 . The semiconductor package as claimed in  claim 1 , wherein the second conductive bump is an oblong shape from the top view. 
     
     
         8 . The semiconductor package as claimed in  claim 1 , wherein the first conductive bump connects to a power pad or ground pad of the semiconductor die. 
     
     
         9 . The semiconductor package as claimed in  claim 1 , wherein the second conductive bump connects to a signal pad of the semiconductor die. 
     
     
         10 . The semiconductor package as claimed in  claim 1 , further comprising:
 a first under bump metallurgy layer pattern disposed between the semiconductor die and the first conductive bump; and   a second under bump metallurgy layer pattern disposed between the semiconductor die and the second conductive bump.   
     
     
         11 . The semiconductor package as claimed in  claim 10 , wherein the first under bump metallurgy layer pattern is a circular shape from the top view. 
     
     
         12 . The semiconductor package as claimed in  claim 10 , wherein the second under bump metallurgy layer pattern is a rectangular shape from the top view. 
     
     
         13 . The semiconductor package as claimed in  claim 10 , further comprising:
 a first conductive pillar connecting to and between the first under bump metallurgy layer pattern and the first conductive bump; and   a second conductive pillar connecting to and between the second under bump metallurgy layer pattern and the second conductive bump.   
     
     
         14 . The semiconductor package as claimed in  claim 13 , wherein the first conductive pillar is a circular shape. 
     
     
         15 . The semiconductor package as claimed in  claim 13 , wherein the second conductive pillar is an oblong shape from the top view. 
     
     
         16 . The semiconductor package as claimed in  claim 13 , wherein an area ratio the first conductive pillar to the second conductive pillar from a top view is larger than 1, and less than or equal to 3. 
     
     
         17 . The semiconductor package as claimed in  claim 1 , further comprising a substrate having a plurality of conductive traces thereon, wherein the first conductive bump and the second conductive bump are bonded onto the conductive traces, respectively. 
     
     
         18 . The semiconductor package as claimed in  claim 1 , further comprising:
 a solder resistance layer disposed on the substrate, away from an overlap region between the substrate and the semiconductor die; and   an underfill material filling a gap between the substrate and the semiconductor