Inversion thickness reduction in high-k gate stacks formed by replacement gate processes

Abstract

A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

1 . A method of forming a transistor device, the method comprising:
 forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate;   forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5;   forming a doped metal layer on the high-k layer;   performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and   forming a metal gate material over the high-k dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the doped metal layer further comprises:
 first and second metallic compound layers that surround a scavenging metal layer, with a material of the first and second metallic compound layers including one of a conductive transition metal nitride and a conductive transition metal carbide; and   the scavenging metal layer comprising a doped metal selected such that a Gibbs free energy change of a chemical reaction, in which an atom constituting a channel combines with a metal oxide material including the doped metal and oxygen to form the doped metal in elemental form and oxide of the atom constituting a channel, is positive.   
     
     
         3 . The method of  claim 2 , wherein the first and second metallic compound layers are selected from the group of TiN, TiC, TaN, TaC, and combinations thereof. 
     
     
         4 . The method of  claim 2 , wherein the doped metal is selected from the group of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, and Ce, and combinations thereof. 
     
     
         5 . The method of  claim 2 , wherein the metal gate material is selected from the group of Al, Ta, TaN, W, WN, Ti and TiN. 
     
     
         6 . The method of  claim 1 , wherein the thermal process is performed at a temperature range of about 400° C. to about 600° C. 
     
     
         7 . The method of  claim 6 , wherein the interfacial layer, the high-k layer, and the doped metal layer are formed between preformed gate sidewall spacers in accordance with a replacement gate scheme. 
     
     
         8 . The method of  claim 6 , further comprising removing the doped metal layer following the thermal process, and prior to forming the metal gate material. 
     
     
         9 . The method of  claim 8 , further comprising performing an anneal in an oxygen ambient environment, at a temperature range of about 350° C. to about 450° C., following removing the doped metal layer and prior to forming the metal gate material. 
     
     
         10 . The method of  claim 6 , wherein the thermal process comprises an anneal performed after formation of the doped metal layer and prior to forming the metal gate material. 
     
     
         11 . The method of  claim 6 , wherein the thermal process comprises forming a sacrificial layer over the doped metal layer, at a deposition temperature range of about 500° C. to about 600° C. 
     
     
         12 . The method of  claim 6 , wherein the sacrificial layer comprises one an amorphous silicon and a polysilicon layer. 
     
     
         13 . The method of  claim 12 , further comprising performing a rapid thermal anneal (RTA) at a temperature range of about 700° C. to about 1000° C., followed by removal of the sacrificial layer prior to forming the metal gate material. 
     
     
         14 . The method of  claim 13 , wherein the RTA further comprises one or more of a flash anneal and a millisecond range laser anneal. 
     
     
         15 . A method of forming a transistor device, the method comprising:
 forming a chemical oxide interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate, and between preformed gate sidewall spacers in accordance with a replacement gate scheme;   forming a high dielectric constant (high-k) layer over an interlevel dielectric layer, on sidewalls of the sidewall spacers, and on the chemical oxide interfacial layer, the high-k layer having a dielectric constant greater than about 7.5;   forming a doped metal layer on the high-k layer;   performing an anneal in an H 2  ambient environment, at a temperature range of about 400° C. to about 600° C., so as to cause the doped metal layer to scavenge oxygen atoms diffused from the chemical oxide interfacial layer interfacial layer such that a final thickness of the chemical oxide interfacial layer interfacial layer is less than about 5 angstroms (Å); and   forming a metal gate material over the high-k dielectric layer, within a recess defined by removal of a dummy gate structure used to form the source and drain regions in the substrate.   
     
     
         16 . The method of  claim 15 , wherein the doped metal layer further comprises:
 first and second metallic compound layers that surround a scavenging metal layer, with a material of the first and second metallic compound layers including one of a conductive transition metal nitride and a conductive transition metal carbide; and   the scavenging metal layer comprising a doped metal selected such that a Gibbs free energy change of a chemical reaction, in which an atom constituting a channel combines with a metal oxide material including the doped metal and oxygen to form the doped metal in elemental form and oxide of the atom constituting a channel, is positive.   
     
     
         17 . The method of  claim 15 , wherein the first and second metallic compound layers are selected from the group of TiN, TiC, TaN, TaC, and combinations thereof. 
     
     
         18 . The method of  claim 15 , wherein the doped metal is selected from the group of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, and Ce, and combinations thereof. 
     
     
         19 . A method of forming a transistor device, the method comprising:
 forming a chemical oxide interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate, and between preformed gate sidewall spacers in accordance with a replacement gate scheme;   forming a high dielectric constant (high-k) layer over an interlevel dielectric layer, on sidewalls of the sidewall spacers, and on the chemical oxide interfacial layer, the high-k layer having a dielectric constant greater than about 7.5;   forming a doped metal layer on the high-k layer;   forming a sacrificial layer over the doped metal layer, at a deposition temperature range of about 500° C. to about 600° C., so as to cause the doped metal layer to scavenge oxygen atoms diffused from the chemical oxide interfacial layer interfacial layer such that a final thickness of the chemical oxide interfacial layer interfacial layer is less than about 5 angstroms (Å);   removing the sacrificial layer; and   forming a metal gate material over the high-k dielectric layer, within a recess defined by removal of a dummy gate structure initially used to form the source and drain regions in the substrate.   
     
     
         20 . The method of  claim 19 , wherein the doped metal layer further comprises:
 first and second metallic compound layers that surround a scavenging metal layer, with a material of the first and second metallic compound layers including one of a conductive transition metal nitride and a conductive transition metal carbide; and   the scavenging metal layer comprising a doped metal selected such that a Gibbs free energy change of a chemical reaction, in which an atom constituting a channel combines with a metal oxide material including the doped metal and oxygen to form the doped metal in elemental form and oxide of the atom constituting a channel, is positive.   
     
     
         21 . The method of  claim 19 , wherein the first and second metallic compound layers are selected from the group of TiN, TiC, TaN, TaC, and combinations thereof. 
     
     
         22 . The method of  claim 19 , wherein the doped metal is selected from the group of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, and Ce, and combinations thereof. 
     
     
         23 . The method of  claim 19 , further comprising performing a rapid thermal anneal (RTA) at a temperature range of about 700° C. to about 1000° C., prior to removal of the sacrificial layer prior to forming the metal gate material. 
     
     
         24 - 26 . (canceled)