Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces

Abstract

Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.

1 . A microelectronic device comprising:
 a substrate;   a first shallow trench isolation structure defined within the substrate, wherein the first shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a first liner oxide is formed within the first shallow trench isolation structure;   a second shallow trench isolation structure defined within the substrate, wherein the second shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a second liner oxide is formed within the second shallow trench isolation structure; and   a device component located (i) on the surface of the substrate and (ii) between the top of the first shallow trench isolation structure and the top of the second shallow trench isolation structure,   wherein each of the rounded bottom surface of the first shallow trench isolation structure and the rounded bottom surface of the second shallow trench isolation structure respectively reduce stress associated with formation of the first liner oxide within the first shallow trench isolation structure and formation of the second liner oxide within the second shallow trench isolation structure.   
     
     
         2 . The microelectronic device of  claim 1 , wherein each of the first shallow trench isolation structure and the second shallow trench isolation structure is filled with a trench oxide. 
     
     
         3 . The microelectronic device of  claim 1 , wherein the device component comprises a transistor. 
     
     
         4 . The microelectronic device of  claim 1 , wherein the microelectronic device comprises a memory device. 
     
     
         5 . The microelectronic device of  claim 1 , wherein:
 the microelectronic device comprises a plurality of shallow trench isolation structures defined within the substrate, wherein the plurality of shallow trench isolation structures includes the first shallow trench isolation structure and the second shallow trench isolation structure, and wherein each of the plurality of shallow trench isolation structures includes (i) a top located at the surface of the substrate and (ii) a bottom surface that has a rounded shape; and   a plurality of device components, wherein each device component of the plurality of device components is located (i) on the surface of the substrate and (ii) between corresponding tops of a corresponding two of the plurality of shallow trench isolation structures,   wherein each of the rounded bottom surfaces of the plurality of shallow trench isolation structures respectively reduce stress associated with formation of the liner oxides within the plurality of shallow trench isolation structures.   
     
     
         6 . The microelectronic device of  claim 5 , wherein each of the plurality of shallow trench isolation structures is filled with a trench oxide. 
     
     
         7 . The microelectronic device of  claim 6 , wherein the plurality of device components comprise a plurality of transistors. 
     
     
         8 . The microelectronic device of  claim 7 , wherein the microelectronic device comprises a memory device. 
     
     
         9 . A method of making a microelectronic device, the method comprising:
 providing a substrate;   forming a first shallow trench isolation structure within the substrate, wherein the first shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a first liner oxide is formed within the first shallow trench isolation structure;   forming a second shallow trench isolation structure within the substrate, wherein the second shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a second liner oxide is formed within the second shallow trench isolation structure; and   forming a device component located (i) on the surface of the substrate and (ii) between the top of the first shallow trench isolation structure and the top of the second shallow trench isolation structure,   wherein each of the rounded bottom surface of the first shallow trench isolation structure and the rounded bottom surface of the second shallow trench isolation structure respectively reduce stress associated with formation of the first liner oxide within the first shallow trench isolation structure and formation of the second liner oxide within the second shallow trench isolation structure.   
     
     
         10 . The method of  claim 9 , wherein forming a first shallow trench isolation structure and forming a second shallow trench isolation structure within the substrate comprises:
 forming two openings within the substrate; and   filling each of the two openings with a trench oxide.   
     
     
         11 . The method of  claim 9 , wherein forming a device component comprises forming a transistor. 
     
     
         12 . The method of  claim 9 , wherein the microelectronic device comprises a memory device. 
     
     
         13 . A method of making a microelectronic device, the method comprising:
 providing a substrate;   forming a plurality of shallow trench isolation structures within the substrate, each of the plurality of shallow trench isolation structures including (i) a top located at a surface of the substrate and (ii) a bottom surface that has a rounded shape, wherein a liner oxide is formed within each shallow trench isolation structure; and   forming a plurality of device components located (i) on the surface of the substrate and (ii) between corresponding tops of a corresponding two of the plurality of shallow trench isolation structures,   wherein each of the rounded bottom surfaces of the plurality of shallow trench isolation structures respectively reduce stress associated with formation of the liner oxides within the plurality of shallow trench isolation structures.   
     
     
         14 . The method of  claim 13 , wherein forming a plurality of shallow trench isolation structures within the substrate comprises:
 forming a plurality of openings within the substrate; and   filling each of the plurality of openings with a trench oxide.   
     
     
         15 . The method of  claim 14 , wherein forming a plurality of device components comprises forming a plurality of transistors. 
     
     
         16 . The method of  claim 15 , wherein the microelectronic device comprises a memory device.