Method for Making a Stackable Package

Abstract

The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

1 . A stackable package, comprising:
 a first chip having at least one through via;   a second chip having an active circuit layer;   a molding compound encapsulating the first chip and the second chip, and having a first surface and a second surface, wherein two ends of the first chip are exposed to the first surface and the second surface of the molding compound respectively, and two ends of the second chip are exposed to the first surface and the second surface of the molding compound respectively;   a first redistribution layer disposed on the second surface of the molding compound for electrically connecting the active circuit layer of the second chip and the at least one through via of the first chip; and   a second redistribution layer disposed on the first surface of the molding compound for electrically connecting the at least one through via of the first chip.   
     
     
         2 . The stackable package as claimed in  claim 1 , wherein the second chip is a known-good die. 
     
     
         3 . The stackable package as claimed in  claim 1 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer and a conductor, the first insulating layer is disposed on a side wall of the hole and defines a first groove, and the conductor fills up the first groove. 
     
     
         4 . The stackable package as claimed in  claim 1 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer, a conductor and a second insulating layer, the first insulating layer is disposed on a side wall of the hole and defines a first groove, the conductor is only disposed on a side wall of the first groove and defines a second groove, and the second insulating layer fills up the second groove. 
     
     
         5 . The stackable package as claimed in  claim 1 , wherein the first redistribution layer comprises a protective layer, a first circuit layer and an under ball metal layer (UBM), the first circuit layer is disposed in the protective layer, the protective layer has a first surface and a second surface, the second surface has at least one second opening, so as to expose part of the first circuit layer, the under ball metal layer (UBM) is disposed in the second opening, and electrically connected to the first circuit layer. 
     
     
         6 . The stackable package as claimed in  claim 1 , wherein the second redistribution layer comprises a protective layer, a second circuit layer and an under ball metal layer (UBM), the second circuit layer is disposed in the protective layer, the protective layer has a first surface and a second surface, the second surface has at least one second opening, so as to expose part of the second circuit layer, the under ball metal layer (UBM) is disposed in the second opening, and electrically connected to the second circuit layer. 
     
     
         7 . A stackable package, comprising:
 a molding compound having a first surface, a second surface, a first through hole and a second through hole;   a first chip disposed in the first through hole of the molding compound, and having a first surface, a second surface and at least one through via, wherein first surface and the second surface of first chip are exposed to the first surface and the second surface of the molding compound respectively;   a second chip disposed in the second through hole of the molding compound, and having a first surface, a second surface and an active circuit layer, wherein first surface and the second surface of second chip are exposed to the first surface and the second surface of the molding compound respectively, and the active circuit layer is exposed to the second surface of the second chip;   a first redistribution layer disposed on the second surface of the molding compound, the second surface of the first chip and the second surface of the second chip, for electrically connecting the active circuit layer of the second chip and the at least one through via of the first chip; and   a second redistribution layer disposed on the first surface of the molding compound, the first surface of the first chip and the first surface of the second chip, for electrically connecting the at least one through via of the first chip.   
     
     
         8 . The stackable package as claimed in  claim 7 , wherein the second chip is a known-good die. 
     
     
         9 . The stackable package as claimed in  claim 7 , wherein the second surface of the molding compound is level with the second surface of the first chip and the second surface of the second chip. 
     
     
         10 . The stackable package as claimed in  claim 7 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer and a conductor, the first insulating layer is disposed on a side wall of the hole and defines a first groove, and the conductor fills up the first groove. 
     
     
         11 . The stackable package as claimed in  claim 7 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer, a conductor and a second insulating layer, the first insulating layer is disposed on a side wall of the hole and defines a first groove, the conductor is only disposed on a side wall of the first groove and defines a second groove, and the second insulating layer fills up the second groove. 
     
     
         12 . The stackable package as claimed in  claim 7 , wherein the first redistribution layer comprises a protective layer, a first circuit layer and an under ball metal layer (UBM), the first circuit layer is disposed in the protective layer, the protective layer has a first surface and a second surface, the second surface has at least one second opening, so as to expose part of the first circuit layer, the under ball metal layer (UBM) is disposed in the second opening, and electrically connected to the first circuit layer. 
     
     
         13 . The stackable package as claimed in  claim 7 , wherein the second redistribution layer comprises a protective layer, a second circuit layer and an under ball metal layer (UBM), the second circuit layer is disposed in the protective layer, the protective layer has a first surface and a second surface, the second surface has at least one second opening, so as to expose part of the second circuit layer, the under ball metal layer (UBM) is disposed in the second opening, and electrically connected to the second circuit layer. 
     
     
         14 . A stacked package, comprising:
 a stackable package, comprising:
 a first chip having at least one through via; 
 a second chip having an active circuit layer; 
 a molding compound encapsulating the first chip and the second chip, and having a first surface and a second surface, wherein two ends of the first chip are exposed to the first surface and the second surface of the molding compound respectively, and two ends of the second chip are exposed to the first surface and the second surface of the molding compound respectively; 
 a first redistribution layer disposed on the second surface of the molding compound for electrically connecting the active circuit layer of the second chip and the at least one through via of the first chip; and 
 a second redistribution layer disposed on the first surface of the molding compound for electrically connecting the at least one through via of the first chip; 
   a second package stacked on the stackable package; and   at least one conductive element disposed between the stackable package and the second package, for electrically connecting the second package and the second redistribution layer of the stackable package;   
     
     
         15 . The stacked package as claimed in  claim 14 , wherein the second chip is a known-good die. 
     
     
         16 . The stacked package as claimed in  claim 14 , further comprising a third package stacked on the second package. 
     
     
         17 . The stacked package as claimed in  claim 14 , further at least one first bump disposed on the first redistribution layer, and electrically connected to the through via of the first chip and the active circuit layer of the second chip by the first redistribution layer. 
     
     
         18 . The stacked package as claimed in  claim 14 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer and a conductor, the first insulating layer is disposed on a side wall of the hole and defines a first groove, and the conductor fills up the first groove. 
     
     
         19 . The stacked package as claimed in  claim 14 , wherein the first chip further comprises at least one hole, the through via comprises a first insulating layer, a conductor and a second insulating layer, the first insulating layer is disposed on a side wall of the hole and defines a first groove, the conductor is only disposed on a side wall of the first groove and defines a second groove, and the second insulating layer fills up the second groove.