Divot-free planarization dielectric layer for replacement gate

Abstract

After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.

1 . A method of forming a semiconductor structure comprising:
 forming a disposable gate structure comprising at least a disposable gate material portion on a semiconductor substrate;   forming a silicon nitride gate spacer on sidewalls of said disposable gate structure;   forming a silicon nitride liner on said silicon nitride gate spacer and over said disposable gate structure;   forming a planarization dielectric layer on said silicon nitride liner;   physically exposing a top surface of said disposable gate material portion by planarizing said planarization dielectric layer and said silicon nitride liner;   forming a gate cavity by removing at least said disposable gate material portion, wherein all topmost surfaces of said silicon nitride spacer, said silicon nitride liner, and said planarization dielectric layer are within a horizontal plane; and   forming a replacement gate structure by filling said gate cavity with a gate dielectric layer and at least one conductive material and removing portions of said gate dielectric layer and said at least one conductive material from above said horizontal plane.   
     
     
         2 . The method of  claim 1 , wherein formation of said gate cavity is effected by at least one etch that does not remove any material from said silicon nitride liner or said planarization dielectric layer, while removing an entirety of said disposable gate structure. 
     
     
         3 . The method of  claim 1 , wherein formation of said gate cavity is effected by at least one wet etch that employs at least one of hydrofluoric acid and ammonium hydroxide. 
     
     
         4 . The method of  claim 1 , wherein, after said forming of said disposable gate structure and prior to said forming of said gate cavity, no semiconductor oxide is present above a bottom surface of said disposable gate material portion, and no semiconductor oxynitride is present above said bottom surface of said disposable gate material portion. 
     
     
         5 . The method of  claim 1 , further comprising planarizing said planarization dielectric layer employing a top surface of said silicon nitride liner as a stopping layer prior to said physically exposing said top surface of said disposable gate material portion. 
     
     
         6 . The method of  claim 1 , wherein said disposable gate material portion comprises a semiconductor material, and said silicon nitride gate spacer is formed directly on sidewalls of said semiconductor material in said disposable gate structure. 
     
     
         7 . The method of  claim 1 , wherein said planarization dielectric layer comprises a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride. 
     
     
         8 . The method of  claim 7 , wherein said planarization dielectric layer is formed by spin-coating of said dielectric material. 
     
     
         9 . The method of  claim 8 , wherein said planarization dielectric layer comprises hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). 
     
     
         10 . The method of  claim 7 , wherein said planarization dielectric layer is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). 
     
     
         11 . The method of  claim 10 , wherein said planarization dielectric layer comprises a dielectric metal oxide material. 
     
     
         12 . The method of  claim 11 , wherein said dielectric metal oxide material is a polycrystalline dielectric metal oxide material having an average grain size in a range from 3 nm to 100 nm. 
     
     
         13 . The method of  claim 1 , wherein said disposable gate structure includes a disposable gate dielectric comprising at least one of silicon oxide and silicon oxynitride. 
     
     
         14 . The method of  claim 13 , wherein said disposable gate material portion comprises a semiconducting material. 
     
     
         15 . The method of  claim 1 , wherein, after forming of said gate cavity and prior to said forming of said replacement gate structure, no semiconductor oxide is present above a bottommost surface of said silicon nitride liner, and no semiconductor oxynitride is present above said bottommost surface of said silicon nitride liner. 
     
     
         16 . The method of  claim 1 , wherein said replacement gate structure comprises:
 a U-shaped gate dielectric in contact with inner sidewalls of one of said at least one silicon nitride gate spacer; and   a gate electrode comprising said at least one conductive material and in contact with inner sidewalls of said U-shaped gate dielectric.   
     
     
         17 . The method of  claim 1 , wherein inner sidewall surfaces of said silicon nitride gate spacer are physically exposed within said gate cavity. 
     
     
         18 .- 25 . (canceled)