Nonvolatile memory cells having phase changeable patterns therein for data storage

Abstract

Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.

What is claimed is: 
     
         1 . A memory device, comprising:
 a word line on a substrate;   a diode on the word line;   a bottom electrode on the diode, the bottom electrode having an L-shape when viewed in cross section;   an interlayer insulating layer in contact with a first side portion of the bottom electrode;   a first insulating pattern in contact with a second side portion of the bottom electrode;   a second insulating pattern in contact with a third side portion of the bottom electrode;   a phase changeable pattern on the bottom electrode; and   a bit line on the phase changeable pattern.   
     
     
         2 . The memory device of  claim 1 , wherein an interface between the phase changeable pattern and the bottom electrode has a line shape when viewed from a plan perspective. 
     
     
         3 . The memory device of  claim 2 , wherein a longitudinal direction of the interface between the phase changeable pattern and the bottom electrode is parallel to a longitudinal direction of the bit line. 
     
     
         4 . The memory device of  claim 1 , wherein a top surface of the bottom electrode is in contact with the phase changeable pattern. 
     
     
         5 . The memory device of  claim 4 , wherein the top surface of the bottom electrode has a line shape when viewed from a plan perspective. 
     
     
         6 . The memory device of  claim 5 , wherein a longitudinal direction of the word line is perpendicular to a longitudinal direction of the top surface of the bottom electrode. 
     
     
         7 . The memory device of  claim 1 , wherein the diode comprises at least one of a titanium nitride layer and a tungsten layer. 
     
     
         8 . The memory device of  claim 1 , further comprising a spacer between the first insulating pattern and an upper portion of the bottom electrode, wherein the spacer comprises an insulating layer. 
     
     
         9 . A memory device, comprising:
 a substrate;   a bottom electrode on the substrate;   a phase changeable pattern in contact with a top surface of the bottom electrode, wherein an interface between the phase changeable pattern and the bottom electrode has a line shape when viewed from a plan perspective; and   a conductive line on the phase changeable pattern,   wherein a longitudinal direction of the interface between the phase changeable pattern and the bottom electrode and a longitudinal direction of the conductive line extend a first direction when viewed from the plan perspective.   
     
     
         10 . The memory device of  claim 9 , wherein the bottom electrode has an L-shape when viewed in cross section. 
     
     
         11 . The memory device of  claim 9 , further comprising:
 an interlayer insulating layer in contact with a first side portion of the bottom electrode;   a first insulating pattern in contact with a second side portion of the bottom electrode; and   second insulating patterns in contact with third side portions of the bottom electrode.   
     
     
         12 . The memory device of  claim 11 , wherein the bottom electrode extends between the second insulating patterns. 
     
     
         13 . The memory device of  claim 11 , wherein the interlayer insulating layer, the first insulating pattern and the second insulating patterns surround the bottom electrode. 
     
     
         14 . The memory device of  claim 11 , further comprising a spacer in contact with a fourth side portion of the bottom electrode, wherein the spacer comprises an insulating layer. 
     
     
         15 . The memory device of  claim 14 , wherein the fourth side portion of the bottom electrode extends higher than the second side portion of the bottom electrode relative to an upper surface of the substrate. 
     
     
         16 . The memory device of  claim 14 , wherein the spacer extends between the first insulating pattern and an upper portion of the bottom electrode. 
     
     
         17 . A memory device, comprising:
 a semiconductor substrate;   a first bottom electrode and a second bottom electrode on the semiconductor substrate;   a first data storage pattern in contact with the first bottom electrode;   a second data storage pattern in contact with the second bottom electrode;   a first bit line on the first data storage pattern; and   a second bit line on the second data storage pattern,   wherein longitudinal directions of a first interface between the first data storage pattern and the first bottom electrode and a second interface between the second data storage pattern and the second bottom electrode are parallel, and   wherein longitudinal directions of top surfaces of the first and second bottom electrodes are parallel to longitudinal directions of the first and second bit lines.   
     
     
         18 . The memory device of  claim 17 , further comprising:
 a first insulating pattern between the first bottom electrode and the second bottom electrode;   a first spacer between the first insulating pattern and an upper portion of the first bottom electrode; and   a second spacer between the first insulating pattern and an upper portion of the second bottom electrode.   
     
     
         19 . The memory device of  claim 17 , wherein the first and second bottom electrodes have an L-shape when viewed in cross section. 
     
     
         20 . The memory device of  claim 17 , wherein the first and second data storage patterns comprise a phase changeable material.