Structure and method for nfet with high k metal gate

Abstract

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.

1 . An integrated circuit, comprising:
 a semiconductor substrate;   an n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and   a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the nFET further comprising a silicide feature formed on the polysilicon feature. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the capping layer includes lanthanum oxide (LaO). 
     
     
         4 . The integrated circuit of  claim 1 , wherein the p work function metal includes titanium nitride (TiN). 
     
     
         5 . The integrated circuit of  claim 1 , wherein the metal material includes aluminum. 
     
     
         6 . The integrated circuit of  claim 1 , wherein each of the nFET and pFET further includes an interfacial layer of silicon oxide disposed between the semiconductor substrate and the high k dielectric layer. 
     
     
         7 . The integrated circuit of  claim 1  further comprising a resistor formed on the semiconductor substrate and having the high k dielectric layer, the p work function metal on the high k dielectric layer, and the polysilicon feature on the p work function metal. 
     
     
         8 . The integrated circuit of  claim 1 , further comprising at least one dummy gate formed on the semiconductor substrate and having the high k dielectric layer, the capping layer on the high k dielectric layer, the p work function metal on the capping layer, and the polysilicon feature on the p work function metal. 
     
     
         9 . A semiconductor structure, comprising:
 a semiconductor substrate;   an n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, a polysilicon layer on the p work function metal, and a silicide feature on the polysilicon layer;   a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal; and   a dummy gate formed on the semiconductor substrate and having the high k dielectric layer, the capping layer on the high k dielectric layer, the p work function metal on the capping layer, and the polysilicon feature on the p work function metal.   
     
     
         10 . The semiconductor structure of  claim 9 , further comprising a resistor formed on the semiconductor substrate and having the high k dielectric layer, the p work function metal on the high k dielectric layer, and the polysilicon layer on the p work function metal. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the capping layer includes lanthanum oxide (LaO). 
     
     
         12 . The semiconductor structure of  claim 9 , wherein the p work function metal includes a material selected from the group consisting of titanium nitride (TiN), tantalum nitride, tungsten nitride (WN) and combination of. 
     
     
         13 . The semiconductor structure of  claim 9 , wherein the metal material includes a metal selected from the group consisting of aluminum, copper, tungsten and combination thereof. 
     
     
         14 . The semiconductor structure of  claim 9 , each of the nFET and pFET further includes an interfacial layer of silicon oxide disposed between the semiconductor substrate and the high k dielectric layer. 
     
     
         15 . The integrated circuit of  claim 9 , wherein the first gate stack, the second gate stack and the dummy gate stack each include gate spacer disposed on respective gate stack sidewalls. 
     
     
         16 . The semiconductor structure of  claim 9 , further comprising an interlayer dielectric (ILD) material formed in gaps of the first gate, the second gate and dummy gate. 
     
     
         17 . A method, comprising
 providing a semiconductor substrate having a first region for an n-type field effect transistor (nFET), a second region for a p-type field effect transistor (pFET) and a third region for a dummy gate;   forming a high k dielectric layer on a semiconductor substrate in the first, second and third regions;   forming a lanthanum oxide capping layer on the high k dielectric layer within the first and second regions;   forming a titanium nitride layer on the lanthanum oxide layer in the first and second regions and on the high dielectric layer in the second region;   forming a polysilicon layer on the titanium layer in the first, second and second regions;   patterning the polysilicon layer, titanium nitride layer, the lanthanum oxide layer and the high k dielectric layer to form a first gate stack in the first region, a second gate stack in the second region and a dummy gate stack in the third region; and   replacing the polysilicon layer in the second region by a metal material.   
     
     
         18 . The method of  claim 16 , wherein the replacing the polysilicon layer in the second region by a metal material includes
 etching the polysilicon layer in the second region, resulting in a gate trench;   depositing the metal material in the gate trench; and   performing a chemical mechanical polishing (CMP) process to the metal material.   
     
     
         19 . The method of  claim 17 , further comprising forming a silicide on the first gate stack in the first region. 
     
     
         20 . The method of  claim 17 , further comprising
 forming source and drain features in the semiconductor substrate by ion implantation after the patterning the polysilicon layer, titanium nitride layer, the lanthanum oxide layer and the high k dielectric layer; and   performing a thermal annealing to the semiconductor substrate to resistor.