Semiconductor device including graded gate stack, related method and design structure

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate; and   a gate structure disposed directly on the substrate, the gate structure including:
 a graded region with a varied material concentration profile; and 
 a metal layer disposed on the graded region. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the graded region includes a first portion proximate the substrate and a second portion proximate the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the graded region contains at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), and zirconium oxide (Zr 2 O 3 ). 
     
     
         4 . The semiconductor device of  claim 1 , wherein a concentration of each material in the graded region varies linearly. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a concentration of each material in the graded region varies exponentially. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another. 
     
     
         7 . A method of forming a semiconductor device, the method comprising:
 providing a substrate; and   forming a graded region directly upon a portion of the substrate, the forming including introducing nitrogen into the graded region to control a varied material concentration profile of the graded region.   
     
     
         8 . The method of  claim 7 , wherein forming the graded region includes:
 forming a first portion proximate the substrate, the first portion containing substantially silicon; and   forming a second portion above the first portion and the substrate, the second portion containing substantially metal.   
     
     
         9 . The method of  claim 7 , wherein forming the graded region includes depositing the graded region in-situ. 
     
     
         10 . The method of  claim 7 , wherein forming the graded region includes:
 depositing a plurality of films on the substrate, the plurality of films having a varied material composition relative one another; and   patterning the plurality of films to form a gate stack.   
     
     
         11 . The method of  claim 7 , wherein the graded region includes at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), and zirconium oxide (Zr 2 O 3 ). 
     
     
         12 . The method of  claim 7 , further comprising annealing the substrate and the graded region to stabilize the graded region. 
     
     
         13 . The method of  claim 7 , wherein forming the graded region includes performing a nitrogen plasma process on the graded region. 
     
     
         14 . The method of  claim 13 , further comprising controlling the varied material concentration profile of the graded region by manipulating at least one of: a temperature of the nitrogen plasma process, a pressure of the nitrogen plasma process, and a duration of the nitrogen plasma process. 
     
     
         15 . The method of  claim 7 , wherein forming the graded region includes performing a rapid thermal ammonia (NH 3 ) annealing process on the graded region. 
     
     
         16 . The method of  claim 15 , further comprising controlling the varied material concentration profile of the graded region by manipulating at least one of: a temperature of the rapid thermal ammonia (NH 3 ) annealing process, a pressure of the rapid thermal ammonia (NH 3 ) annealing process, and a duration of the rapid thermal ammonia (NH 3 ) annealing process. 
     
     
         17 . A design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing a semiconductor device, the design structure comprising:
 a substrate; and   a gate structure disposed directly on the substrate, the gate structure including:
 a graded region with a varied material concentration profile; and 
 a metal layer disposed on the graded region. 
   
     
     
         18 . The design structure of  claim 17 , wherein the graded region includes a first portion proximate the substrate and a second portion proximate the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal. 
     
     
         19 . The design structure of  claim 17 , wherein the graded region contains at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), and zirconium oxide (Zr 2 O 3 ). 
     
     
         20 . The design structure of  claim 17 , wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another.