Semiconductor substrate with transistors having different threshold voltages

Abstract

A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

1 . A semiconductor integrated circuit, comprising:
 a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate;   the first FET device having raised source/drain (RSD) structures grown at a first height and the second FET device having RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device, wherein an effective channel length of the second FET device is longer than an effective channel length of the first FET device such that extension structures of the first FET device extend further beneath a gate structure thereof in a lateral direction with respect to extension structures of the second FET device, and wherein a gate length of the second FET device is the same as a gate length of the first FET device.   
     
     
         2 . (canceled) 
     
     
         3 . The semiconductor integrated circuit of  claim 1 , wherein an epitaxy height of the RSD structures of the first FET device ranges from about 3 nm to about 30 nm. 
     
     
         4 . The semiconductor integrated circuit of  claim 1 , wherein an epitaxy height of the RSD structures of the second FET device ranges from about 6 nm to about 35 nm. 
     
     
         5 . The semiconductor integrated circuit of  claim 1 , wherein the semiconductor substrate comprises an extremely thin silicon-on-insulator (ETSOI) substrate. 
     
     
         6 . The semiconductor integrated circuit of  claim 5 , comprising at least one gate dielectric layer that is formed on the ETSOI layer, wherein gate structures of the first and second FET devices are formed on the at least one gate dielectric layer. 
     
     
         7 . The semiconductor integrated circuit of  claim 6 , wherein a gate length of the gate structures, and a gate insulator thickness of the at least one gate dielectric layer of the first and second FET devices are the same. 
     
     
         8 . The semiconductor integrated circuit of  claim 6 , wherein the at least one gate dielectric layer is selected from the group consisting of silicon oxynitride (SiON) and a high-k dielectric. 
     
     
         9 . The semiconductor integrated circuit of  claim 6 , further comprising a first set of spacers disposed on lateral sidewalls of gate structures of the first and second FET devices, wherein the first set of spacers are located on opposing lateral sides of the gate structures. 
     
     
         10 . The semiconductor integrated circuit of  claim 9 , further comprising a second set of spacers disposed on opposing lateral sides of the first set of spacers. 
     
     
         11 . The semiconductor integrated circuit of  claim 6 , wherein each of the gate structures includes a gate silicide contact. 
     
     
         12 . The semiconductor integrated circuit of  claim 1 , wherein the RSD structures of the first and second FET devices includes a faceted configuration. 
     
     
         13 . The semiconductor integrated circuit of  claim 1 , wherein the semiconductor integrated circuit is a system-on-a-chip (SOC) integrated circuit. 
     
     
         14 . The semiconductor integrated circuit of  claim 1 , wherein the RSD structures of the first and second FET devices includes a silicide contact. 
     
     
         15 . The semiconductor integrated circuit of  claim 1 , wherein channel regions of the first and second FET devices are undoped. 
     
     
         16 . The semiconductor integrated circuit of  claim 6 , wherein a PC pitch that is a pitch between two substantially parallel gates, remains constant between a plurality of FETs.