Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device

Abstract

A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

What is claimed is: 
     
         1 . A method of fabricating a prompt-shift semiconductor device comprising:
 providing at least one field effect transistor within a memory area of a semiconductor substrate, said at least one field effect transistor including a patterned gate region and an extension dielectric spacer located on sidewalls of said patterned gate region;   performing an extension ion implant without a mask into said semiconductor substrate and on both sides of the patterned gate region, said extension ion implant uses an ion dosage that is less than about 5E14 atoms/cm 2 ;   performing a halo ion implant without a mask into said semiconductor substrate and on both sides of the patterned gate region, said halo ion implant uses an ion dosage of greater than about 1E13 atoms/cm 2 ;   forming a source/drain dielectric spacer onto exposed surfaces of said extension dielectric spacer; and   forming source and drain regions on both sides of said patterned gate region using said source/drain dielectric spacers as an implant mask.   
     
     
         2 . The method of  claim 1  wherein said halo ion implant comprises a first halo ion implant step using a first halo ion, and a second halo ion implant step using a second halo ion. 
     
     
         3 . The method of  claim 1  wherein said at least one field effect transistor is an nFET, and said performing said extension ion implant includes selecting an extension dopant ion from Group VA of the Periodic Table of Elements and said performing said halo ion implant includes selecting a halo dopant ion from Group IIIA of the Periodic Table of Elements. 
     
     
         4 . The method of  claim 1  wherein said performing said extension ion implant includes using an energy from about 5 to about 5 KeV and an implant angle of from 0° to about 30° as measured from a surface of said semiconductor substrate. 
     
     
         5 . The method of  claim 1  wherein said performing said halo ion implant includes implanting a first halo ion using an energy from about 50 to about 200 KeV and an implant angle of from about 10° to about 30° as measured from a surface of said semiconductor substrate. 
     
     
         6 . The method of  claim 5  wherein said performing said halo ion implant includes a second halo implant that comprises implanting a second halo ion using an energy from about 5 to about 50 KeV and an implant angle of from about 10° to about 30° as measured from a surface of said semiconductor substrate. 
     
     
         7 . The method of  claim 1  wherein said extension ion implant forms an extension region on both sides of the patterned gate region, each extension region has a terminal point that is located beneath said extension dielectric spacer and not aligned to an edge of said extension dielectric spacer or an edge of the patterned gate region. 
     
     
         8 . The method of  claim 1  wherein said halo implant forms a halo implant region on both sides of the patterned gate region, each halo implant region has a terminal point located directly beneath said extension dielectric spacer and not aligned to an edge of said extension dielectric spacer or an edge of the patterned gate region. 
     
     
         9 . The method of  claim 1  wherein said source and drain regions have a terminal point that is located beneath said source/drain dielectric spacer and not aligned to any edge of the source/drain dielectric spacer. 
     
     
         10 . The method of  claim 1  further comprising forming an oxide region by thermal oxide on exposed sidewalls of said patterned gate region prior to forming said extension dielectric spacer. 
     
     
         11 . The method of  claim 3  wherein said extension dopant ion is arsenic and said halo ion implant includes In as said halo dopant ion. 
     
     
         12 . The method of  claim 11  further comprising B as another halo dopant ion. 
     
     
         13 . The method of  claim 4  wherein said implant angle of said extension ion implant is from 5° to about 10°. 
     
     
         14 . The method of  claim 4  wherein said energy of said extension ion implant is from 10 KeV to 20 KeV. 
     
     
         15 . The method of  claim 4  wherein said ion dosage of said extension ion implant is from 1E13 atoms/cm 2  to less than about 5E14 atoms/cm 2 . 
     
     
         16 . The method of  claim 5  wherein said implant angle of said halo ion implant is from 20° to about 30°. 
     
     
         17 . The method of  claim 5  wherein said energy of said halo ion implant is from 110 KeV to 140 KeV. 
     
     
         18 . The method of  claim 1  wherein said ion dosage of said halo ion implant is from 3E13 atoms/cm 2  to less than about 5E14 atoms/cm 2 . 
     
     
         19 . The method of  claim 1  wherein said performing said extension ion implant forms an extension region having an extension dopant concentration of less than about 1E20 atoms/cm 3 . 
     
     
         20 . The method of  claim 1  wherein said performing said halo ion implant forms a halo implant region having a halo dopant concentration of greater than about 5E18 atoms/cm 3 .