Reverse Conducting IGBT

Abstract

A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body. The first and second emitter regions are arranged between the drift region and a first electrode and are each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source region and the body region. A floating parasitic region of the first conductivity type is disposed outside the cell region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body;   a first electrode, wherein the first emitter region and the second emitter region are arranged between the drift region and the first electrode and are each connected to the first electrode;   a cell region comprising at least one device cell, the at least one device cell comprising a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric;   a second electrode electrically connected to the source region and the body region of the at least one device cell;   at least one first parasitic region of the first conductivity type disposed outside the cell region; and   wherein the at least one first parasitic region is floating.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 an edge termination structure; and   wherein the at least one first parasitic region is part of the edge termination structure.   
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a gate pad or gate via electrically connected to the gate electrode, arranged above the semiconductor body and distant to the cell region; and   wherein the at least one first parasitic region is at least partially arranged below the gate pad or gate via in the semiconductor body.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a second parasitic region distant to the at least one first parasitic region and outside the cell region.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the second parasitic region adjoins the gate dielectric of at least one device cell. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 at least one planar conductor arranged above the semiconductor body outside the cell region and electrically connected to the gate electrode.   
     
     
         7 . The semiconductor device of  claim 6 , further comprising:
 an edge termination structure arranged outside the cell region, the edge termination structure comprising at least one field plate; and   wherein the at least one planar conductor is further connected to the at least one first field plate.   
     
     
         8 . The semiconductor device of  claim 6 , further comprising:
 a gate pad or gate via arranged outside the cell region and above a first surface of the semiconductor body; and   wherein the at least one planar conductor is further connected to the gate pad or gate via.   
     
     
         9 . The semiconductor device of  claim 6 , further comprising:
 a first trench electrode and a second trench electrode electrically connected to the at least one planar conductor, each arranged in a trench and dielectrically insulated from the semiconductor body.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the first and second trench electrodes surround the cell region. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the at least one first parasitic region adjoins the trench with the first trench electrode. 
     
     
         12 . The semiconductor device of  claim 9 , wherein a section of the drift region extends to a first surface of the semiconductor body between the first and second trench electrodes. 
     
     
         13 . The semiconductor device of  claim 9 , wherein a section of the at least one first parasitic region extends to a first surface of the semiconductor body between the first and second trench electrodes. 
     
     
         14 . The semiconductor device of  claim 1 , further comprising:
 a plurality of device cells; and   a floating semiconductor region of the first conductivity type in the cell region between the individual device cells.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the floating semiconductor region adjoins a first surface of the semiconductor body. 
     
     
         16 . The semiconductor device of  claim 14 ,
 wherein the gate electrode of each device cell is arranged in a trench that surrounds the body region of the device cell, and   wherein the gate electrodes of neighboring device cells are electrically connected through conductors arranged above the semiconductor body.   
     
     
         17 . The semiconductor device of  claim 14 , wherein the at least one first parasitic region is electrically connected to the floating semiconductor region. 
     
     
         18 . The semiconductor device of  claim 14 , further comprising:
 a second parasitic region of the first conductivity type distant to the at least one first parasitic region; and   wherein at least one of the first and second parasitic regions is electrically connected to the floating semiconductor region.   
     
     
         19 . The semiconductor device of  claim 1 , further comprising:
 a plurality of device cells in the cell region;   an edge region of the cell region; and   wherein device cells along the edge region of the cell region do not comprise a source region.   
     
     
         20 . The semiconductor device of  claim 1 ,
 wherein a length of the drift region is in a current flow direction, the current flow direction being a direction in which charge carriers flow through the drift region when the semiconductor device is in an on-state, and   wherein a distance between the at least one first parasitic region and the second emitter region in a direction perpendicular to the current flow direction corresponds to at least the length of the drift region.