Chip arrangements and a method for forming a chip arrangement

Abstract

A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.

What is claimed is: 
     
         1 . A chip arrangement comprising:
 a chip comprising at least one electrically conductive contact;   a passivation material formed over the at least one electrically conductive contact;   an encapsulation material formed over the passivation material;   one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes;   electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.   
     
     
         2 . The chip arrangement according to  claim 1 ,
 wherein the passivation material comprises at least one from the following group of materials, the group of materials consisting of: polyimide, epoxy, silicon nitride, silicon oxide, aluminum oxide, aluminum nitride.   
     
     
         3 . The chip arrangement according to  claim 1 ,
 wherein the encapsulation material comprises at least one from the following group of materials, the group consisting of: an electrically insulating material, filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, a thermoplastic material, filler particles, fiber-reinforced laminate, fiber-reinforced polymer laminate, fiber-reinforced polymer laminate with filler particles.   
     
     
         4 . The chip arrangement according to  claim 1 ,
 wherein the passivation material comprises a thickness ranging from about 1 nm to about 50 μm.   
     
     
         5 . The chip arrangement according to  claim 1 ,
 wherein the encapsulation material comprises a thickness ranging from about 10 μm to about 300 μm.   
     
     
         6 . The chip arrangement according to  claim 1 ,
 wherein the passivation material covers a surface of the at least one electrically conductive contact and a side of the chip not covered by the at least one electrically conductive contact.   
     
     
         7 . The chip arrangement according to  claim 1 ,
 wherein at least a portion of the electrically conductive material directly contacts the passivation material; and   wherein at least a further portion of the electrically conductive material directly contacts the encapsulation material.   
     
     
         8 . The chip arrangement according to  claim 1 ,
 wherein the passivation material formed between the one or more holes directly contacts the electrically conductive material filling the one or more holes.   
     
     
         9 . The chip arrangement according to  claim 1 ,
 wherein the electrically conductive material comprises at least one material, element or alloy from the following group of materials, the group consisting of: copper, aluminum, silver, tin, gold, zinc, nickel.   
     
     
         10 . The chip arrangement according to  claim 1 ,
 wherein at least part of the electrically conductive material is formed over the encapsulation material.   
     
     
         11 . The chip arrangement according to  claim 1 ,
 wherein the chip is disposed over a chip carrier; and   wherein at least one of the passivation material and the encapsulation material is formed over the chip carrier.   
     
     
         12 . The chip arrangement according to  claim 11 ,
 wherein the chip carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group consisting of: copper, nickel, iron, copper alloy, nickel alloy, iron alloy.   
     
     
         13 . The chip arrangement according to  claim 11 ,
 wherein the chip carrier comprises a printed circuit board or a direct copper bonded substrate.   
     
     
         14 . The chip arrangement according to  claim 1 ,
 wherein the at least one electrically conductive contact is a plurality of electrically conductive contacts.   
     
     
         15 . A chip arrangement comprising:
 a chip comprising at least one electrically conductive contact;   a passivation material formed over the at least one electrically conductive contact;   an encapsulation material formed over the passivation material;   one or more holes formed through the encapsulation material and the passivation material, wherein the one or more holes are filled with electrically conductive material electrically connected to the at least one electrically conductive contact;   wherein the passivation material substantially covers a surface of the at least one electrically conductive contact except in regions wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.   
     
     
         16 . The chip arrangement according to  claim 15 ,
 wherein the passivation material comprises at least one from the following group of materials, the group of materials consisting of: polyimide, epoxy, silicon nitride, silicon oxide, aluminum oxide, aluminum nitride.   
     
     
         17 . The chip arrangement according to  claim 15 ,
 wherein the encapsulation material comprises at least one from the following group of materials, the group consisting of: an electrically insulating material, filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, a thermoplastic material, filler particles, fiber-reinforced laminate, fiber-reinforced polymer laminate, fiber-reinforced polymer laminate with filler particles.   
     
     
         18 . The chip arrangement according to  claim 15 ,
 wherein the passivation material at least partially surrounds the one or more holes and covers a side of the chip not covered by the at least one electrically conductive contact.   
     
     
         19 . The chip arrangement according to  claim 15 ,
 wherein at least a portion of the electrically conductive material directly contacts the passivation material; and   wherein at least a further portion of the electrically conductive material directly contacts the encapsulation material.   
     
     
         20 . The chip arrangement according to  claim 15 ,
 wherein the electrically conductive material comprises at least one from the following group of materials, the group consisting of: copper, aluminum, silver, tin, gold, zinc, nickel, and an alloy of one or more materials of the group.   
     
     
         21 . The chip arrangement according to  claim 15 ,
 wherein the chip is disposed over a chip carrier; and   wherein at least one of the passivation material and encapsulation material is formed over the chip carrier.   
     
     
         22 . The chip arrangement according to  claim 21 ,
 wherein the chip carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group consisting of: copper, nickel, iron, copper alloy, nickel alloy, iron alloy.   
     
     
         23 . The chip arrangement according to  claim 21 ,
 wherein the chip carrier comprises a printed circuit board or a direct copper bonded substrate.   
     
     
         24 . A method for forming a chip arrangement, the method comprising:
 forming a passivation material over at least one electrically conductive contact of a chip;   forming an encapsulation material over the passivation material;   forming one or more holes through the encapsulation material and the passivation material; and   providing an electrically conductive material within the one or more holes, electrically connecting the electrically conductive material to the at least one electrically conductive contact.   
     
     
         25 . The method according to  claim 24 , further comprising
 disposing the chip over a chip carrier before or after forming the passivation material over at least one electrically conductive contact of a chip.   
     
     
         26 . The method according to  claim 24 , further comprising
 performing a roughening process on the chip carrier after forming the passivation material and before forming the encapsulation material over the passivation material.   
     
     
         27 . The method according to  claim 24 ,
 wherein forming one or more holes through the encapsulation material and the passivation material comprises forming one or more holes through the encapsulation material and the passivation material by at least one method from the following group of methods, the group consisting of: laser drilling and mechanical drilling.   
     
     
         28 . The method according to  claim 24 ,
 wherein providing an electrically conductive material within the one or more holes comprises at least one of filling the one or more holes with electrically conductive material and growing electrically conductive material within the one or more holes.