Apparatus and Method for Memory Device

Abstract

An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer.

What is claimed is: 
     
         1 . An apparatus comprising:
 a gate stack formed over a substrate, wherein the gate stack comprises:
 a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate; and 
 a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure; 
   a first drain/source region; and   a first recess formed between a top surface of the first drain/source region and the second dielectric layer.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 a second drain/source region formed on an opposite side of the gate stack from the first drain/source region; and   a second recess formed between a top surface of the second drain/source region and the second dielectric layer.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the first dielectric layer is a tunneling layer of a flash memory device.   
     
     
         4 . The apparatus of  claim 1 , wherein:
 the second dielectric layer is a blocking layer of a flash memory device.   
     
     
         5 . The apparatus of  claim 1 , wherein:
 the first recess is of a height in a range from 5 Angstroms to 200 Angstroms.   
     
     
         6 . The apparatus of  claim 1 , wherein:
 the first gate structure comprises a floating gate of a flash memory device.   
     
     
         7 . The apparatus of  claim 1 , wherein:
 the second gate structure comprises a control gate of a flash memory device.   
     
     
         8 . A device comprising:
 a tunneling layer formed over a substrate;   a floating gate formed over the tunneling layer;   a blocking layer is formed over the floating gate, wherein the block layer is free of lateral undercuts;   a control gate formed over the blocking layer;   a first step between a top surface of a first drain/source region and the tunneling layer; and   a second step between a top surface of a second drain/source region and the tunneling layer, wherein the second drain/source region is on an opposite side of the tunneling layer from the first drain/source region.   
     
     
         9 . The device of  claim 8 , wherein:
 the blocking layer comprises SiO 2 —Si 3 N 4 —SiO 2  (ONO).   
     
     
         10 . The device of  claim 8 , further comprising:
 a gate stack formed by the tunneling layer, the floating gate, the blocking layer and the control gate, wherein the gate stack is covered by an oxide layer.   
     
     
         11 . The device of  claim 8 , wherein:
 the first step is of a height in a range from 5 Angstroms to 200 Angstroms.   
     
     
         12 . The device of  claim 8 , wherein:
 the second step is of a height in a range from 5 Angstroms to 200 Angstroms.   
     
     
         13 . The device of  claim 8 , wherein:
 the floating gate comprises doped polysilicon.   
     
     
         14 . The device of  claim 8 , wherein:
 the control gate comprises doped polysilicon.   
     
     
         15 . A method comprising:
 forming a gate stack on a substrate;   applying an oxygen flush process to the gate stack and the substrate to form a first oxide layer on the substrate;   applying an ion implantation process to the gate stack and the substrate, wherein through the ion implantation process, a first drain/source region and a second drain/source region are formed on opposite sides of the gate stack;   applying a pre-cleaning process to the gate stack and the substrate, wherein the first oxide layer is removed after the pre-cleaning process; and   growing an oxide layer on the gate stack.   
     
     
         16 . The method of  claim 15 , further comprising:
 implementing the oxygen flush process by using oxygen plasma in a dry etch chamber.   
     
     
         17 . The method of  claim 15 , further comprising:
 depositing a tunneling layer on the substrate;   depositing a floating gate on the tunneling layer;   depositing a blocking layer on the floating gate; and   depositing a control gate on the blocking layer.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming a SiO 2 —Si 3 N 4 —SiO 2  layer between the floating gate and the control gate, wherein the SiO 2 —Si 3 N 4 —SiO 2  layer is free of lateral undercuts.   
     
     
         19 . The method of  claim 15 , further comprising:
 removing the first oxide layer; and   forming a first recess between a top surface of the first drain/source region and a bottom of the gate stack.   
     
     
         20 . The method of  claim 15 , further comprising:
 removing the first oxide layer; and   forming a second recess between a top surface of the second drain/source region and a bottom of the gate stack.