US2014175670A1PendingUtilityA1

Stacked die package

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Assignee: CHEAH BOK ENGPriority: Sep 10, 2007Filed: Feb 26, 2014Published: Jun 26, 2014
Est. expirySep 10, 2027(~1.2 yrs left)· nominal 20-yr term from priority
Inventors:Bok Eng CheahShanggar PeriamanKooi Chi OoiYen Hsiang Chew
H10W 90/297H10W 90/722H10W 90/754H10W 74/15H10W 90/724H10W 90/734H10W 72/07331H10W 72/30H10W 20/20H10W 90/00H01L 25/0657H01L 23/481H01L 25/18
53
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Claims

Abstract

The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Claims

exact text as granted — not AI-modified
What is claimed: 
     
         1 . An assembly comprising:
 first and second semiconductor die structures each including a front side and a backside, the front side including an active region;   a plurality of vias in each of the first and second semiconductor die structures, the vias forming electrical connections between the active region and the backside; and   the first and second semiconductor die structures being stacked together wherein the vias in the first semiconductor die structure are substantially aligned with the vias in the second semiconductor die structure.   
     
     
         2 . The assembly of  claim 1 , wherein the first die structure is disposed on a substrate and wherein the second die is coupled to the substrate by a wire bond. 
     
     
         3 . The assembly of  claim 1 , wherein the first die structure is a first central processing unit and wherein the second die structure is a second central processing unit. 
     
     
         4 . The assembly of  claim 1 , wherein the first die structure is a central processing unit die and wherein the second die structure is a memory chip. 
     
     
         5 . The assembly of  claim 1 , further including a third die structure disposed on the second die structure. 
     
     
         6 . The assembly of  claim 1 , wherein the first die structure is disposed on a substrate; wherein the first die is a first central processing unit; and wherein the second die structure is a second central processing unit. 
     
     
         7 . The assembly of  claim 1 , wherein the first die structure is disposed on a substrate; wherein the first die is a central processing unit; and wherein the second die structure is a memory chip. 
     
     
         8 . The assembly of  claim 1 , wherein the first die structure is disposed on a substrate; wherein the wherein the first die structure is a memory chip; and wherein the second die structure is a memory chip. 
     
     
         9 . An assembly comprising:
 first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions thereon;   a plurality of vias in each of the first and second semiconductor die structures, the vias forming electrical connections between the active region and the backside metal regions; and   the first and second semiconductor die structures being stacked together wherein the vias in the first semiconductor die structure are substantially aligned with the vias in the second semiconductor die structure.   
     
     
         10 . The assembly of  claim 9 , wherein the first die structure is disposed on a substrate and wherein the second die is coupled to the substrate by a wire bond. 
     
     
         11 . The assembly of  claim 9 , wherein the first die structure is a first central processing unit and wherein the second die structure is a second central processing unit. 
     
     
         12 . The assembly of  claim 9 , wherein the first die structure is a central processing unit die and wherein the second die structure is a memory chip. 
     
     
         13 . The assembly of  claim 9 , further including a third die structure disposed on the second die structure. 
     
     
         14 . The assembly of  claim 9 , wherein the first die structure is disposed on a substrate; wherein the first die is a first central processing unit; and wherein the second die structure is a second central processing unit. 
     
     
         15 . The assembly of  claim 9 , wherein the first die structure is disposed on a substrate; wherein the first die is a central processing unit; and wherein the second die structure is a memory chip. 
     
     
         16 . The assembly of  claim 9 , wherein the first die structure is disposed on a substrate; wherein the wherein the first die structure is a memory chip; and wherein the second die structure is a memory chip. 
     
     
         17 . An assembly comprising:
 first and second semiconductor die structures each including a front side and a backside, the front side including an active region;   at least one via in each of the first and second semiconductor die structures, the vias forming electrical connections between the active region and the backside; and   the first and second semiconductor die structures being stacked together wherein the at least one via in the first semiconductor die structure is electrically connected with the vias in the second semiconductor die structure.   
     
     
         18 . The assembly of  claim 17 , wherein the first die structure is disposed on a substrate and wherein the second die is coupled to the substrate by a wire bond. 
     
     
         19 . The assembly of  claim 17 , wherein the first die structure is a first central processing unit and wherein the second die structure is a second central processing unit. 
     
     
         20 . The assembly of  claim 17 , wherein the first die structure is a central processing unit die and wherein the second die structure is a memory chip. 
     
     
         21 . The assembly of  claim 17 , further including a third die structure disposed on the second die structure. 
     
     
         22 . The assembly of  claim 17 , wherein the first die structure is disposed on a substrate; wherein the first die is a first central processing unit; and wherein the second die structure is a second central processing unit. 
     
     
         23 . The assembly of  claim 17 , wherein the first die structure is disposed on a substrate; wherein the first die is a central processing unit; and wherein the second die structure is a memory chip. 
     
     
         24 . The assembly of  claim 17 , wherein the first die structure is disposed on a substrate; wherein the wherein the first die structure is a memory chip; and wherein the second die structure is a memory chip.

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