Inventor · disambiguated record
Shanggar Periaman
Also filed as: PERIAMAN SHANGGAR
19 granted patents·5 pending applications·632 citations·filing 2005–2017
95Inventor score
Top patents by PatentIndex Score
24 records- 0198US7279795B2Stacked die semiconductor packageINTEL CORP·Filed 2005·Granted Oct 9, 2007·353 cites·15 claims
- 0297US8198716B2Die backside wire bond technology for single or stacked die packagePERIAMAN SHANGGAR·Filed 2007·Granted Jun 12, 2012·92 cites·19 claims
- 0396US8987896B2High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming sameCHEAH BOK ENG·Filed 2010·Granted Mar 24, 2015·31 cites·3 claims
- 0496US7692278B2Stacked-die packages with silicon vias and surface activated bondingINTEL CORP·Filed 2006·Granted Apr 6, 2010·46 cites·9 claims
- 0594US9136251B2Method to enable controlled side chip interconnection for 3D integrated packaging systemCHEAH BOK ENG·Filed 2012·Granted Sep 15, 2015·16 cites·30 claims
- 0691US8044497B2Stacked die packageINTEL CORP·Filed 2007·Granted Oct 25, 2011·18 cites·20 claims
- 0790US9812425B2Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for sameINTEL CORP·Filed 2016·Granted Nov 7, 2017·5 cites·18 claims
- 0889US9478524B2Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for sameINTEL CORP·Filed 2015·Granted Oct 25, 2016·5 cites·7 claims
- 0989US8697495B2Stacked die packageCHEAH BOK ENG·Filed 2011·Granted Apr 15, 2014·9 cites·12 claims
- 1088US8281229B2Firmware verification using system memory error check logicCHEW YEN HSIANG·Filed 2008·Granted Oct 2, 2012·19 cites·20 claims
- 1181US7400033B1Package on package design to improve functionality and efficiencyINTEL CORP·Filed 2006·Granted Jul 15, 2008·10 cites·15 claims
- 1280US9778688B2Flexible system-in-package solutions for wearable devicesINTEL CORP·Filed 2014·Granted Oct 3, 2017·5 cites·24 claims
- 1380US8110930B2Die backside metallization and surface activated bonding for stacked die packagesPERIAMAN SHANGGAR·Filed 2007·Granted Feb 7, 2012·10 cites·19 claims
- 1476US7773504B2Bandwidth allocation for network packet trafficINTEL CORP·Filed 2007·Granted Aug 10, 2010·6 cites·18 claims
- 1570US10396038B2Flexible packaging architectureINTEL CORP·Filed 2014·Granted Aug 27, 2019·3 cites·11 claims
- 1668US9721878B2High density second level interconnection for bumpless build up layer (BBUL) packaging technologyCHEAH BOK ENG·Filed 2012·Granted Aug 1, 2017·2 cites·12 claims
- 1763US10403604B2Stacked package assembly with voltage reference planeINTEL CORP·Filed 2015·Granted Sep 3, 2019·1 cites·18 claims
- 1863US9646953B2Integrated circuit packaging techniques and configurations for small form-factor or wearable devicesINTEL CORP·Filed 2014·Granted May 9, 2017·1 cites·22 claims
- 1953US2014175670A1Stacked die packageCHEAH BOK ENG·Filed 2014·Application pending·0 cites
- 2050US2018145014A1High density second level interconnection for bumpless build up layer (bbul) packaging technologyINTEL CORP·Filed 2017·Application pending·0 cites
- 2147US7743181B2Quality of service (QoS) processing of data packetsINTEL CORP·Filed 2007·Granted Jun 22, 2010·0 cites·20 claims
- 2245US2015201497A1High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming sameINTEL CORP·Filed 2015·Application pending·0 cites
- 2343US2008315388A1Vertical controlled side chip connection for 3d processor packagePERIAMAN SHANGGAR·Filed 2007·Application pending·0 cites
- 2439US2012319293A1Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die packageCHEAH BOK ENG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →