Method for manufacturing multi-gate transistor device

Abstract

A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

What is claimed is: 
     
         1 . A method for manufacturing multi-gate transistor device, comprising:
 providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer formed thereon, and the gate layer covering a portion of the patterned semiconductor layer;   forming a multiple insulating layer on the semiconductor substrate, the multiple insulating layer covering the patterned semiconductor layer and the gate layer, wherein the multiple insulating layer sequentially has a first insulating layer and a second insulating layer;   performing a first etching process to remove a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer;   removing the second spacer to expose a portion of the first insulating layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, the first insulating layer still covering the patterned semiconductor layer; and   removing the exposed first insulating layer to expose the patterned semiconductor layer.   
     
     
         2 . The method for manufacturing multi-gate transistor device according to  claim 1 , wherein an etching rate of the first insulating layer is different from an etching rate of the second insulating layer. 
     
     
         3 . The method for manufacturing multi-gate transistor device according to  claim 2 , wherein the first insulating layer comprises silicon nitride and the second insulating layer comprises silicon oxide. 
     
     
         4 . The method for manufacturing multi-gate transistor device according to  claim 1 , wherein the first insulating layer comprises a thickness between 50 angstroms and 100 angstroms. 
     
     
         5 . The method for manufacturing multi-gate transistor device according to  claim 1 , wherein the first etching process comprises an anisotropic etching process. 
     
     
         6 . The method for manufacturing multi-gate transistor device according to  claim 1 , further comprising a second etching process performed to remove the exposed first insulating layer to expose the patterned semiconductor layer. 
     
     
         7 . The method for manufacturing multi-gate transistor device according to  claim 6 , wherein the second etching process comprises an isotropic etching process. 
     
     
         8 . The method for manufacturing multi-gate transistor device according to  claim 1 , wherein the third spacer comprises the first insulating layer and the second insulating layer. 
     
     
         9 . The method for manufacturing multi-gate transistor device according to  claim 1 , further comprising forming an epitaxial source/drain in the patterned semiconductor layer after exposing the patterned semiconductor layer.