Semiconductor device and method of manufacturing same

Abstract

A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a semiconductor substrate having a first region including a memory cell and a second region including a logic circuit;   first and second impurity regions formed in the first region;   a first gate electrode formed over the first region and formed over a region which is arranged between the first and second impurity regions;   third and fourth impurity regions formed in the second region;   a second gate electrode formed over the second region and formed over a region which is arranged between the third and fourth impurity regions;   a first insulating layer formed over the first and second regions so as to cover the first and second gate electrode;   first, second, third and fourth contact plugs formed in the first insulating layer and electrically connected to the first, second, third and fourth impurity regions, respectively;   a second insulating layer formed over the first insulating layer;   a lower electrode of a capacitor formed in the second insulating layer and connected to the first contact plug;   a dielectric film of the capacitor formed on the lower electrode;   an upper electrode of the capacitor formed on the dielectric film;   a fifth contact plug formed in the second insulating layer and directly connected to the second contact plug;   a sixth contact plug formed in the second insulating layer and directly connected to the third contact plug;   a first interconnection formed in the second insulating layer and connected to the fifth contact plug; and   a second interconnection formed in the second insulating layer and connected to the sixth contact plug,   wherein the fifth contact plug and the first interconnection are formed integrally each other and include a copper film, and   wherein the sixth contact plug and the second interconnection are formed integrally each other and include a copper film.   
     
     
         3 . A semiconductor device according to the  claim 2 ,
 wherein the first interconnection composes a bit line of the memory cell.   
     
     
         4 . A semiconductor device according to the  claim 2 ,
 wherein the memory cell is a DRAM.