Channel-Last Methods for Making FETS

Abstract

Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.

What is claimed is: 
     
         1 . A field effect transistor (FET) comprising
 a substrate,   a first layer disposed above the substrate, the first layer being operable as a gate electrode,   a second layer disposed above the first layer, the second layer comprising a dielectric material,   a third layer disposed above the second layer, the third layer comprising a semiconductor, and   a fourth layer disposed above the third layer, the fourth layer comprising one or more conductive materials and operable as source and drain electrodes.   
     
     
         2 . The FET of  claim 1 , further comprising a fifth layer disposed between the second layer and the third layer, wherein the fifth layer is operable as an interface layer. 
     
     
         3 . The FET of  claim 1 , further comprising a sixth layer disposed between the third layer and the source and drain electrodes, wherein the sixth layer is operable as a passivation layer. 
     
     
         4 . The FET of  claim 1 , wherein the second layer comprises a high-κ dielectric. 
     
     
         5 . The FET of  claim 1 , wherein the third layer comprises Ge. 
     
     
         6 . The FET of  claim 1 , wherein the third layer comprises a III-V semiconductor. 
     
     
         7 . The FET of  claim 1 , wherein the third layer comprises graphene. 
     
     
         8 . The FET of  claim 1 , wherein the third layer is substantially strain-free and free of threading defects. 
     
     
         9 . The FET of  claim 1 , wherein the third layer has a thickness of less than 10 nm. 
     
     
         10 . The FET of  claim 1 , wherein the third layer has a thickness of between about 1 nm and about 1.5 nm. 
     
     
         11 . The FET of  claim 1 , wherein a separation between the source and drain electrodes is approximately the same as the width of the gate electrode. 
     
     
         12 . The FET of  claim 1 , wherein the source, drain, and gate electrodes each comprise one or more metals. 
     
     
         13 . The FET of  claim 1 , wherein the first layer is a conformal layer on a trench formed in the substrate surface. 
     
     
         14 . A method of forming a field-effect transistor (FET), the method comprising
 forming a first layer above a substrate, the first layer being operable as a gate electrode;   after forming the first layer, forming a second layer above the first layer, the second layer comprising a dielectric material;   after forming the second layer, forming a third layer above the second layer, the third layer comprising a semiconductor; and   after forming the third layer, forming a fourth layer above the third layer, the fourth layer comprising one or more conductive materials to function as source and drain electrodes.   
     
     
         15 . The method of  claim 14 , further comprising forming a fifth layer on the second layer, wherein the fifth layer is formed after forming the second layer and before forming the third layer, wherein the fifth layer is operable as an interface layer. 
     
     
         16 . The method of  claim 14 , further comprising forming a sixth layer on the third layer, wherein the sixth layer is formed after forming the third layer and before forming the fourth layer, wherein the sixth layer is operable as a passivation layer. 
     
     
         17 . The method of  claim 14 , wherein the second layer comprises a high-κ dielectric. 
     
     
         18 . The method of  claim 14 , wherein the third layer comprises Ge. 
     
     
         19 . The method of  claim 14 , wherein the third layer comprises a III-V semiconductor or graphene. 
     
     
         20 . The method of  claim 14 , wherein the third layer is substantially strain-free and free of threading defects.