Semiconductor package and semiconductor device

Abstract

The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor package, comprising:
 a substrate including a top patterned conductive layer at a top surface of the substrate, the top patterned conductive layer defining a plurality of top pads;   a plurality of conductive components positioned on corresponding ones of the top pads;   a chip positioned on the top surface of the substrate and electrically connected to the top patterned conductive layer; and   a molding compound encapsulating the chip, the top patterned conductive layer, and the plurality of conductive components, wherein:   the molding compound extends laterally to edges of the substrate;   the molding compound at a central portion of the substrate has a first height, and the central portion extends beyond a periphery of the chip;   the molding compound in a border area between the central portion and the edges of the substrate has a second height less than half of the first height; and   the molding compound in the border area exposes and is coplanar with a top surface of at least one of the plurality of conductive components.   
     
     
         21 . The semiconductor package of  claim 20 , wherein the top pads are arranged in multiple rows surrounding the chip. 
     
     
         22 . The semiconductor package of  claim 20 , wherein the conductive components are arranged in multiple rows surrounding the chip. 
     
     
         23 . The semiconductor package of  claim 20 , wherein the conductive components include solder. 
     
     
         24 . The semiconductor package of  claim 20 , wherein the bottom patterned conductive layer is substantially coplanar with the bottom surface of the substrate. 
     
     
         25 . The semiconductor package of  claim 20 , wherein each of the conductive components has a hemispherical shape. 
     
     
         26 . The semiconductor package of  claim 20 , wherein a top surface extending across the border area includes cut marks. 
     
     
         27 . A semiconductor device, comprising: a semiconductor package including a chip, conductive components, and a molding compound including a central portion and a border portion, wherein:
 the central portion fully encapsulates the chip, and the central portion has a first height greater than the height of the chip;   the border portion extends between the central portion and an external periphery of the package, and wherein:
 the border portion has a second height less than the first height, a top surface across the extent of the border portion includes marks incurred by removal of a portion of the molding compound, and 
 the top surface exposes the conductive components embedded in the molding compound. 
   
     
     
         28 . The semiconductor device of  claim 27 , wherein the second height is less than half of the first height. 
     
     
         29 . The semiconductor device of  claim 27 , further comprising solder balls at a lower surface of the semiconductor package. 
     
     
         30 . The semiconductor device of  claim 27 , further comprising a substrate and a patterned conductive layer, wherein the chip is positioned on the substrate and is electrically connected to the patterned conductive layer, and the conductive components are positioned on pads defined by the patterned conductive layer. 
     
     
         31 . The semiconductor device of  claim 27 , wherein the semiconductor package is a first package, further comprising a second package stacked on the first package, and the second package is electrically coupled to the first package through the conductive components. 
     
     
         32 . The semiconductor device of  claim 31 , wherein the second package is electrically coupled to the first package through the conductive components by way of a plurality of solder balls positioned at a lower surface of the second package and contacting respective ones of the conductive components. 
     
     
         33 . A method of forming a stackable package, comprising:
 positioning conductive elements on respective top pads in a top surface of a substrate;   mounting a chip on the top surface of the substrate;   applying a molding compound over the top surface of the substrate to a first height, including applying the molding compound over the chip, the top pads, and the conductive elements; and   cutting the molding compound in a border area around a circumference of the package to a second height less than the first height, wherein the second height is less than an original height of the conductive elements, and wherein the conductive elements are exposed in the border area by the cutting.   
     
     
         34 . The method of  claim 33 , wherein the cutting includes removing a part of each of the conductive elements, such that at least one of the conductive elements has a hemispherical shape. 
     
     
         35 . The method of  claim 33 , wherein subsequent to the cutting, the molding compound in a central area has the first height.