Structure and method of high-performance extremely thin silicon on insulator complementary metal-oxide-semiconductor transistors with dual stress buried insulators

Abstract

A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

1 . A semiconductor device comprising:
 a bulk substrate;   a silicon layer deposited on top of said bulk substrate;   a plurality of shallow trench isolations structures formed in said bulk substrate for isolating active areas for forming an NFET and PFET for forming a gate channel region for respective NFET and PFET device;   a NFET having a source region, a drain region, and a gate formation;   a PFET having a source region, a drain region, and a gate formation;   an insulator layer, comprising a stressed oxide or nitride, deposited in between said bulk substrate and said silicon layer of said NFET;   a second insulator layer, comprising either an stressed oxide or nitride, deposited in between said bulk substrate and said silicon layer of said PFET.   
     
     
         2 . The semiconductor device as in  claim 1 , wherein the plurality shallow trench isolations are filled with either a tensile stressed oxide or a compressive stressed oxide to further enhance the strain of the semiconductor device. 
     
     
         3 . The semiconductor device as in  claim 1 , wherein the insulator layer deposited inside the substrate of the NFET is tensile stressed oxide or nitride; and
 the second insulator layer deposited inside the substrate of the PFET is compressive stressed oxide or nitride.   
     
     
         4 . The semiconductor device as in  claim 1 , wherein said gate formation of the NFET has different high-k dielectric and gate metal than the PFET high-k dielectric and gate metal. 
     
     
         5 . The semiconductor device as in  claim 4 , wherein the insulator layer deposited inside the substrate of the NFET is tensile stressed oxide or nitride, and;
 the second insulator layer deposited inside the substrate of the PFET is compressive stressed oxide or nitride.   
     
     
         6 . A semiconductor device comprising:
 a bulk substrate;   a buried oxide (BOX) layer deposited on top of said bulk substrate;   an extremely thin silicon on insulator (ETSOI) layer deposited on top of said BOX layer;   a plurality of shallow trench isolations structures formed in said bulk substrate for isolating active areas for forming an NFET device and PFET for forming a gate channel region for respective NFET and PFET device;   a NFET having a source region, a drain region, and a gate formation;   a PFET having a source region, a drain region, and a gate formation;   an insulator layer, comprising a stressed oxide or nitride, deposited in between said bulk substrate and said ETSOI layer of said NFET; and   a second insulator layer, comprising either an stressed oxide or nitride, deposited in between said bulk substrate and said ETSOI layer of said PFET.   
     
     
         7 . The semiconductor device as in  claim 6 , wherein the plurality shallow trench isolations are filled with either a tensile stressed oxide or a compressive stressed oxide to further enhance the strain of the semiconductor device. 
     
     
         8 . The semiconductor device as in  claim 6 , wherein the insulator layer deposited inside the substrate of the NFET is tensile stressed oxide or nitride, and;
 the second insulator layer deposited inside the substrate of the PFET is compressive stressed oxide or nitride.   
     
     
         9 . The semiconductor device as in  claim 6 , wherein said gate formation of the NFET has different high-k dielectric and gate metal than the PFET high-k dielectric and gate metal. 
     
     
         10 . The semiconductor device as in  claim 9 , wherein the insulator layer deposited inside the substrate of the NFET is tensile stressed oxide or nitride, and;
 the second insulator layer deposited inside the substrate of the PFET is compressive stressed oxide or nitride.   
     
     
         11 . A method of forming a semiconductor device, the method comprising the steps of:
 providing a bulk substrate layer, a buried oxide (BOX) layer disposed on said substrate layer, a extremely thin silicon on insulator (ETSOI) layer disposed on said buried oxide (BOX) layer;   forming shallow trench isolation regions in a substrate to isolate active ETSOI regions for forming a first FET region and a second FET region;   forming a hard mask over said second FET region;   recessing the bulk substrate layer in said first FET region;   depositing a first layer of silicon germanium (SiGe) in the recess of said first FET region;   depositing a layer of silicon on top of said first layer of SiGe in the recess of said first FET region;   forming a first gate dielectric layer on said first FET region and a first gate conductor formed atop of said first gate dielectric layer on said first FET region to form a first gate electrode structure;   recessing the shallow trench isolation regions surrounding said first FET region to the bottom of the first layer of SiGe in the recess of the first FET region;   removing said first layer of SiGe, which creates a first air gap;   filling said first air gap with a first insulator layer comprising either stressed oxide or stressed nitride;   filling said recessed shallow trench isolations regions surrounding said first FET region with an oxide, such that an enhanced strain is applied to the first FET region;   removing the hard mask from the second FET region;   forming a second hard mask or a soft mask over the first FET region;   recessing the bulk substrate layer of the second FET region;   depositing a second layer of SiGe in the recess of the second FET region and depositing a silicon layer on top of said second layer of SiGe layer;   forming a second gate dielectric layer on said second FET region and a second gate conductor formed atop of said second gate dielectric layer on the second FET device;   recessing said shallow trench isolation regions surrounding said second FET region to the bottom of the second layer of SiGe;   removing said second layer of SiGe in the recess of the second FET region, which creates a second air gap;   filling said second air gap with a second insulator comprising either stressed oxide or stressed nitride;   filling the recessed shallow trench isolation regions surrounding the second FET region with an oxide, such that an enhanced strain is applied to the second FET region; and   removing said second hard mask layer or soft mask from said first FET region.   
     
     
         12 . The method as in  claim 11 , wherein said first gate electrode structure comprises a different high-k dielectric and gate metal and the second gate electrode structure comprises a different high-k dielectric and gate metal. 
     
     
         13 . The method as in  claim 12  wherein the step of filling the shallow trench isolation regions surrounding said first FET region and surrounding said second FET region further comprises the steps of:
 filling the shallow trench isolation regions surrounding said first FET region with either a tensile stressed oxide or compressive stressed oxide; and 
 filling the shallow trench isolation regions surrounding said second FET region with either a tensile stressed oxide or a compressive stressed oxide. 
 
     
     
         14 . A method for forming a semiconductor device comprising:
 providing a bulk substrate layer;   forming shallow trench isolation regions to isolate active regions for forming a first FET region and a second FET region;   forming a hard mask over said bulk substrate;   recessing said bulk substrate layer on both FET regions;   depositing a silicon germanium (SiGe) layer in the recesses of both FET regions;   depositing a silicon layer on top of said SiGe layer;   forming a gate dielectric layer on both FET regions and a corresponding gate conductor formed atop of said gate dielectric layer on both FET regions;   recessing said shallow trench isolation regions surrounding both FET regions down to the bottom of said SiGe layer;   forming a hard mask over said second FET region;   removing said SiGe layer from said first FET region, which creates a first air gap;   filling said first air gap with an insulator comprising either stressed oxide or stressed nitride;   filling said shallow trench isolation regions with an oxide, such that an enhanced strain is applied to the first FET region;   removing said hard mask layer from said second FET region;   forming a hard mask over said first FET region;   removing the SiGe layer from said second FET region, which creates a second air gap;   filling said second air gap with an insulator comprising either stressed oxide or stressed nitride; and   removing said hard mask layer from said first FET region.   
     
     
         15 . The method as in  claim 14 , wherein the step of filling the shallow trench isolation regions further comprises the step of:
 filling the shallow trench isolation regions with either a tensile stressed oxide or compressive stressed oxide.   
     
     
         16 . A method for forming a semiconductor device comprising:
 providing a bulk substrate layer, a buried oxide (BOX) layer disposed on said substrate layer, a extremely thin silicon on insulator (ETSOI) layer disposed on said buried oxide (BOX) layer;   forming shallow trench isolation regions to isolate active regions for forming a first FET region and a second FET region;   forming a hard mask over said bulk substrate;   recessing said bulk substrate layer on both FET regions;   depositing a layer of silicon germanium (SiGe) in the recesses of both FET regions;   depositing a silicon layer on top of said SiGe layer;   forming a gate dielectric layer on both FET regions and a corresponding gate conductor formed atop of said gate dielectric layer on both FET regions;   recessing said shallow trench isolation regions surrounding both FET regions down to the bottom of said SiGe layer;   forming a hard mask over said second FET region;   removing said SiGe layer from said first FET region, which creates a first air gap;   filling said air gap with an insulator comprising either stressed oxide or stressed nitride;   filling said shallow trench isolation with an oxide, such that an enhanced strain is applied to the first FET region;   removing said hard mask layer from said second FET region;   forming a hard mask over said first FET region;   removing the SiGe layer from said second FET region, which creates a second air gap;   filling said second air gap with an insulator comprising either stressed oxide or stressed nitride; and   removing said hard mask layer from said first FET region.   
     
     
         17 . The method as in  claim 16 , wherein the step of filling the shallow trench isolation regions further comprises the step of:
 filling the shallow trench isolation regions with either a tensile stressed oxide or compressive stressed oxide.