Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes

Abstract

Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming an underfill material layer between and covering metal pillar/solder bump pairs of the integrated circuits. The method also involves forming a mask layer on the underfill material layer. The method also involves laser scribing mask layer and the underfill material layer to provide scribe lines exposing portions of the semiconductor wafer between the integrated circuits. The method also involves removing the mask layer. The method also involves, subsequent to removing the mask layer, plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the second insulating layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves, subsequent to the plasma etching, thinning but not removing the underfill material layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

1 .- 14 . (canceled) 
     
     
         15 . An apparatus, comprising:
 a substrate carrier comprising a tape frame surrounding a dicing tape;   a semiconductor wafer disposed on a portion of the dicing tape, the semiconductor wafer comprising a front surface having a plurality of integrated circuits thereon;   a first insulating layer disposed between lower portions of metal pillar/solder bump pairs of the integrated circuits; and   a second insulating layer disposed on the first insulating layer, between and covering upper portions of the metal pillar/solder bump pairs.   
     
     
         16 . The apparatus of  claim 15 , further comprising:
 a mask layer disposed on the second insulating layer.   
     
     
         17 . The apparatus of  claim 16 , wherein a thickness of the mask layer is approximately in the range of 1-30 microns. 
     
     
         18 . The apparatus of  claim 15 , further comprising:
 scribe lines disposed in the first and second insulating layers, the scribe lines exposing portions of the semiconductor wafer between the integrated circuits.   
     
     
         19 . The apparatus of  claim 15 , wherein the first insulating layer comprises a molding compound, and wherein the second insulating layer comprises an underfill material layer. 
     
     
         20 . The apparatus of  claim 15 , wherein the first insulating layer comprises a thick polyimide passivation layer, and wherein the second insulating layer comprises an underfill material layer. 
     
     
         21 .- 25 . (canceled)