US2015340301A1PendingUtilityA1

Substrateless power device packages

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Assignee: ALPHA & OMEGA SEMICONDUCTORPriority: Oct 29, 2010Filed: Aug 4, 2015Published: Nov 26, 2015
Est. expiryOct 29, 2030(~4.3 yrs left)· nominal 20-yr term from priority
Inventors:Tao FengZhiqiang NiuYuping GongRuisheng WuPing HuangLei ShiYueh-Se Ho
H10W 72/07653H10W 20/0245H10W 74/00H10W 72/0198H10W 72/877H10W 72/886H10W 72/881H10W 72/926H10W 72/944H10W 72/9445H10W 72/9415H10W 72/29H10W 72/9413H10W 72/952H10W 72/942H10W 72/59H10W 72/9226H10W 72/923H10W 72/691H10W 72/07636H10W 72/07336H10W 72/352H10W 90/726H10W 90/736H10W 70/481H10W 70/466H10W 20/20H10W 74/129H10W 74/014H10P 72/7422H10P 72/7416H10P 72/744H10P 72/743H10P 72/74H10P 54/00H10W 90/766H10W 72/01251H10W 90/811H10W 90/00H10W 74/016H10W 74/15H10W 74/012H10W 74/01H10W 72/60H10W 72/20H10W 70/442H10W 70/40H10W 20/069H10P 72/7402H10D 84/83H10D 62/117H10D 30/63H01L 29/7827H01L 23/3114H01L 24/14H01L 27/088H01L 23/481
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Claims

Abstract

A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A vertical conductive power semiconductor device comprising:
 a substrate;   a top metal layer located on a top surface of the substrate;   solder bumps deposited on top of the top metal layer; and   wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed.   
     
     
         2 . The device of  claim 1  wherein the solder bumps are connected to the top metal layer by a under bump metallization (UBM) layer. 
     
     
         3 . The device of  claim 1 , further comprising a back metal layer formed on a backside of the substrate. 
     
     
         4 . The device of  claim 3  wherein the back metal layer includes a bottom drain electrode and the top metal layer includes source and gate electrodes. 
     
     
         5 . The device of  claim 1  wherein the substrate includes an epitaxial layer located on a top side of the substrate. 
     
     
         6 . The device of  claim 1  wherein a total thickness of the substrate is less than about 25 microns. 
     
     
         7 . The device of  claim 1 , wherein the substrate includes a common drain, and the device includes more than one vertical conduction metal oxide semiconductor field effect transistor (MOSFET). 
     
     
         8 . The device of  claim 1  wherein the vertical conductive power semiconductor device comprises a chip scale package (CSP). 
     
     
         9 . The device of  claim 8  wherein the CSP includes one or more through substrate vias (TSV) filled with a conductive material electrically connecting the bottom electrode to the top side of the device. 
     
     
         10 . The device of  claim 9  wherein molding coats the backside of the vertical conductive power semiconductor device. 
     
     
         11 . The device of  claim 8  wherein the CSP further comprises a through substrate via (TSV) filled with solder that electrically connect the bottom electrode to the top side of the device. 
     
     
         12 . The device of  claim 11  wherein the CSP includes back connections routed along the sides of the CSP.

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