Silicon Interposer Sndwich Structure for ESD, EMI, and EMC Shielding and Protection

Abstract

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

1 . A process for providing ESD or EMI or EMC shielding or protection for an integrated circuit electronic device comprising positioning said device in a cage comprising an interposer sandwich structure comprising a top interposer and a bottom interposer enclosing said device, an attaching structure for attaching said device to said bottom interposer, and an interconnection structure connecting said top interposer to said bottom interposer. 
     
     
         2 . The process of  claim 1  wherein said attaching structure for attaching said device to said bottom interposer comprise small metal bumps and said interconnection structure comprises large metal bumps extending from said top interposer and fused with small metal bumps extending from said bottom interposer. 
     
     
         3 . The process of  claim 1  wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large solder bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer. 
     
     
         4 . The process of  claim 1  wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large copper bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer. 
     
     
         5 . The process of  claim 1  wherein said interposers are selected from silicon interposers, ceramic interposers and polymeric interposers and combinations thereof. 
     
     
         6 . The process of  claim 1  wherein said interposers comprise silicon interposers. 
     
     
         7 . The process of  claim 1  wherein said top interposer is also directly connected to a chip carrier. 
     
     
         8 . The process of  claim 1  wherein said top interposer includes a blanket metal coating on at least one of the bottom or top surfaces of said top interposer. 
     
     
         9 . The process of  claim 1  wherein said attaching structure for attaching said device to said bottom interposer comprises electrical connections to an electrical ground or bias. 
     
     
         10 . The process of  claim 1  wherein said top interposer comprises connections to a chip carrier. 
     
     
         11 . The process of  claim 10  wherein said connections to said chip carrier comprises connections to an electrical ground or bias. 
     
     
         12 . The process of  claim 1  comprising a plurality of said devices connected to said bottom interposer wherein said top interposer is operatively associated with less than all of said devices to provide selective functional isolation of said devices for shielding for maximum miniaturization. 
     
     
         13 . The process of  claim 1  comprising a thermal interface material operatively associated with said device to provide rapid heat dissipation from said device. 
     
     
         14 . The process of  claim 12  comprising a thermal interface material operatively associated with said devices to provide rapid heat dissipation from said devices. 
     
     
         15 . A process for forming a cage structure to provide ESD, EMI and EMC shielding and protection of integrated circuit device in 3D packaging by forming said cage as a sandwich structure comprising interposers including top and bottom interposers around said integrated circuit device in which metallized shielding is incorporated into both said top and bottom interposers. 
     
     
         16 . The process of  claim 15  further providing TSV's for interconnection of said metallized shielding to ground or voltage as required electrically, and providing said bottom interposer in said sandwich connected by TSV's and solder connections to said chip carrier package, and said top interposer connecting peripherally by TSV's beyond the outline of said integrated circuit device to said bottom interposer to connect electrically to said chip carrier to provide said cage as a miniature localized cage around said device that preserves the scale of integration and miniaturization of said integrated circuit device. 
     
     
         17 . The process of  claim 15  further providing multiple integrated circuit devices comprising a miniaturized sandwich package structure in which multiple integrated circuit devices are placed adjacent to one another on the same interposer with TSV's in which one or more top interposers are provided to isolate ESD or EMI or EMC sensitive devices from one another in close proximity in said miniaturized sandwich package structure. 
     
     
         18 . The process of  claim 15  providing said interposer sandwich structure as a structure comprising two interposers enclosing said integrated circuit device that includes a solder bump size hierarchy with smaller solder bumps or other interconnection structure attaching said integrated circuit device to said bottom interposer, and larger solder bumps or other interconnection structure connecting said top interposer with said bottom interposer, or directly with said chip carrier, wherein said other interconnection structure comprises copper post bumps or equivalent metal post bumps. 
     
     
         19 . The process of  claim 18  further providing said metal post bumps to extend from either said top interposer or said bottom interposer toward a solder bump on the opposite interposer for connecting said top interposer and said bottom interposer by soldering. 
     
     
         20 . The process of  claim 19  further providing a structure whose height is substantially the same whether employing solder bumps or metal post bumps and the ratio of the heights of said larger bumps to said smaller bumps is about 3:1. 
     
     
         21 . The process of  claim 20  wherein the combined height of said bumps is about 50 μm (microns). 
     
     
         22 . The process of  claim 15  of providing said top interposer with a blanket metal coating on said bottom or top surface and said connections to said bottom interposer or said chip carrier is selected from an electrical ground or bias. 
     
     
         23 . The process of  claim 15  further providing one or more devices connected to said bottom interposer are provided with shielding with a top interposer selectively to provide functional isolation for shielding or protection for maximum miniaturization. 
     
     
         24 . The process of  claim 15  further providing thermal interface material dispensed on the back of said integrated circuit device prior to joining said top interposer in order to provide for rapid heat dissipation from said integrated circuit device.