Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

Abstract

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor substrate;   an insulating structure disposed above the semiconductor substrate;   a semiconductor layer disposed over and directly on the insulating structure;   a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on both sides of the channel region, wherein the semiconductor layer is under the source/drain regions but not under the channel region, the semiconductor layer comprising a semiconductor material different from the semiconductor body; and   a gate electrode stack surrounding the channel region with a portion disposed on the insulating structure directly below the channel region, and laterally adjacent to the semiconductor layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the insulating structure comprises a global insulating layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the insulating structure comprises one or more isolation pedestals. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the semiconductor body comprises greater than approximately 70% germanium. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising:
 a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer extends underneath each of the pair of spacers.   
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 a pair of conducting contacts, one contact disposed on and partially surrounding the source region, and the other contact disposed on and partially surrounding the drain region.   
     
     
         7 . The semiconductor structure of  claim 1 , further comprising:
 one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.   
     
     
         8 . The semiconductor structure of  claim 1 , wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode. 
     
     
         9 . A semiconductor structure, comprising:
 a semiconductor substrate;   an insulating structure disposed above the semiconductor substrate;   a semiconductor layer disposed over and directly on the insulating structure;   a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on both sides of the channel region, wherein the semiconductor layer is under the channel region but not under the source/drain regions, the semiconductor layer comprising a semiconductor material different from the semiconductor body;   a gate electrode stack partially surrounding the channel region; and   a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the insulating structure directly below the channel region, and laterally adjacent to the semiconductor layer.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the insulating structure comprises a global insulating layer. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the insulating structure comprises one or more isolation pedestals. 
     
     
         12 . The semiconductor structure of  claim 9 , wherein the semiconductor body comprises greater than approximately 70% germanium. 
     
     
         13 . The semiconductor structure of  claim 9 , further comprising:
 a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer extends underneath each of the pair of spacers.   
     
     
         14 . The semiconductor structure of  claim 9 , further comprising:
 one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.   
     
     
         15 . The semiconductor structure of  claim 9 , wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode. 
     
     
         16 . A semiconductor structure, comprising:
 a semiconductor substrate;   an insulating structure disposed above the semiconductor substrate;   a semiconductor layer disposed over and directly on the insulating structure;   a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on either side of the channel region, wherein the semiconductor layer is not under the channel region and not under the source/drain regions, the semiconductor layer comprising a semiconductor material different from the semiconductor body;   a gate electrode stack surrounding the channel region with a portion disposed on the insulating structure directly below the channel region;   a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the insulating structure; and   a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer is disposed underneath each of the pair of spacers and laterally adjacent to a portion of the gate electrode stack and a portion of each of the conducting contacts.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein the insulating structure comprises a global insulating layer. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein the insulating structure comprises one or more isolation pedestals. 
     
     
         19 . The semiconductor structure of  claim 16 , further comprising:
 one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.   
     
     
         20 . The semiconductor structure of  claim 16 , wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode.