Semiconductor die, semiconductor wafer and method for manufacturing the same

Abstract

A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor die, comprising:
 a semiconductor body having a first surface, a second surface and a side surface extending between the first surface and the second surface; and   an insulating layer disposed on the first surface and the side surface of the semiconductor body, the insulating layer comprising a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later, the insulating layer including a step structure.   
     
     
         22 . The semiconductor die of  claim 21 , wherein at least one corner of the second insulating layer is arcuate from a top view. 
     
     
         23 . The semiconductor die of  claim 21 , wherein the first insulating layer is disposed on the first surface and the side surface of the semiconductor body, and an area of the second insulating layer is smaller than an area of the first insulating layer from a top view. 
     
     
         24 . The semiconductor die of  claim 23 , wherein there is a gap between a side surface of the second insulating layer and a side surface of the first insulating layer. 
     
     
         25 . The semiconductor die of  claim 24 , wherein the gap extends around a periphery of the semiconductor die. 
     
     
         26 . The semiconductor die of  claim 25 , wherein a width of the gap varies around the periphery of the semiconductor die. 
     
     
         27 . The semiconductor die of  claim 21 , further comprising a conductive circuit layer electrically connected to the first surface of the semiconductor body, the conductive circuit layer comprising at least one pad. 
     
     
         28 . The semiconductor die of  claim 27 , wherein the conductive circuit layer further comprises a patterned circuit layer and at least one conductive via, the patterned circuit layer comprises the pad, and the conductive via connects the patterned circuit layer and the first surface of the semiconductor body. 
     
     
         29 . The semiconductor die of  claim 28 , further comprising at least one conductive bump electrically connected to a respective pad. 
     
     
         30 . A semiconductor wafer, comprising:
 a semiconductor body defining at least one trench recessed from a first surface of the semiconductor body; and   an insulating layer disposed on the first surface of the semiconductor body and on a side surface of the trench, the insulating layer defining at least one groove in the trench, wherein the insulating layer includes a step structure.   
     
     
         31 . The semiconductor wafer of  claim 30 , wherein the trench does not penetrate through the semiconductor body. 
     
     
         32 . The semiconductor wafer of  claim 30 , wherein a bottom surface of the trench is exposed from the insulating layer. 
     
     
         33 . The semiconductor wafer of  claim 30 , wherein the insulating layer comprises a first insulating layer and a second insulating layer disposed over the first insulating layer, wherein at least one corner of the second insulating layer is arcuate from a top view. 
     
     
         34 . The semiconductor wafer of  claim 30 , wherein the insulating layer further defines a trough over the groove, and a width of the trough is greater than a width of the groove. 
     
     
         35 . The semiconductor wafer of  claim 34 , wherein the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is disposed on the first surface of the semiconductor body and the side surface of the trench and defines the groove in the trench, the second insulating layer is disposed on the first insulating layer and defines the trough. 
     
     
         36 . The semiconductor wafer of  claim 30 , further comprising a conductive circuit layer electrically connected to the first surface of the semiconductor body, the conductive circuit layer comprising at least one pad. 
     
     
         37 . The semiconductor wafer of  claim 36 , further comprising at least one conductive bump electrically connected to a respective pad. 
     
     
         38 . A semiconductor die, comprising:
 a semiconductor body having a first surface, a second surface and a side surface extending between the first surface and the second surface; and   an insulating layer disposed on the first surface of the semiconductor body, the insulating layer comprising a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later, the insulating layer including a step structure.   
     
     
         39 . The semiconductor die of  claim 38 , wherein an area of the second insulating layer is smaller than an area of the first insulating layer from a top view. 
     
     
         40 . The semiconductor die of  claim 39 , wherein there is a gap between a side surface of the second insulating layer and a side surface of the first insulating layer.