Three dimensional integrated circuit

Abstract

A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.

1 . A method comprising:
 implanting ions into a first substrate having dielectric structures and conductive structures, the ions traveling through the plurality of conductive structures and the plurality of dielectric structures to define a cleave plane in the first substrate; and   subjecting a portion of the cleave plane to energy sufficient to remove an upper portion of the first substrate that includes the plurality of conductive structures and the plurality of dielectric structures from a lower bulk substrate material.   
     
     
         2 . The method of  claim 1 , wherein the conductive structures include regions doped with ions. 
     
     
         3 . The method of  claim 2 , wherein the doped regions are comprised in transistor devices, and the plurality of dielectric structures include gate dielectric layers. 
     
     
         4 . The method of  claim 2 , wherein the transistor devices are CMOS transistor devices. 
     
     
         5 . The method of  claim 2 , wherein the transistor devices are field effect transistors that include respective gate dielectric layers. 
     
     
         6 . The method of  claim 2 , wherein the ions are implanted through a plurality of interconnect layers coupled to the plurality of transistor devices. 
     
     
         7 . The method of  claim 1 , wherein the cleave region is subjected to greater than 1 MeV of energy. 
     
     
         8 . The method of  claim 1 , wherein the cleave region is subjected to greater than 500 KeV of energy. 
     
     
         9 . The method of  claim 8 , wherein the ions travel through at least eight copper interconnect layers. 
     
     
         10 . The method of  claim 1 , wherein the implantation is performed while keeping the first substrate at a temperature of 500 degrees Celsius or less. 
     
     
         11 . The method of  claim 10 , wherein the implantation is performed while keeping the first substrate at a temperature of 250 degrees Celsius or less. 
     
     
         12 . The method of  claim 11 , wherein the implantation is performed while keeping the first substrate at a temperature of 150 degrees Celsius or less. 
     
     
         13 . The method of  claim 1 , wherein the ions are implanted through a plurality of MEMS devices included with the first substrate. 
     
     
         14 . The method of  claim 1 , wherein the conductive structures include a plurality of interconnect layers. 
     
     
         15 . The method of  claim 14 , wherein the plurality of interconnect layers includes 3 to 15 metal interconnect layers. 
     
     
         16 . The method of  claim 15 , wherein the plurality of metal interconnect layers includes 8 to 15 interconnect layers. 
     
     
         17 . The method of  claim 16 , wherein the 3 to 15 interconnect layers are copper interconnect layers. 
     
     
         18 . The method of  claim 1 , wherein the conductive structures include copper vias, and ends of the copper vias are exposed at the cleave plane. 
     
     
         19 . The method of  claim 18 , wherein a cleave side of the upper portion of the first substrate is bonded to a second substrate. 
     
     
         20 . The method of  claim 19 , wherein the copper vias of the first substrate are coupled to conductive structures of the second substrate. 
     
     
         21 . The method of  claim 1 , wherein the cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers. 
     
     
         22 . The method of  claim 21 , wherein a plurality of the stacked IC layers are formed by implanting ions through conductive and dielectric structures to form respective cleave planes and separating bulk substrate layers along the respective cleave planes. 
     
     
         23 . The method of  claim 22 , wherein the stacked IC layers are bonded to one another by bonding cleave sides of the layers to circuit sides of the layers. 
     
     
         24 . The method of  claim 23 , wherein the cleave sides of the layers are polished before bonding to the circuit sides of the layers. 
     
     
         25 . The method of  claim 23 , wherein the stacked IC layers are bonded to one another by bonding circuit sides together so that metal interconnect layers of the stacked layers are electrically coupled to one another. 
     
     
         26 . The method of  claim 20 , further comprising:
 depositing a dielectric layer to form a bonding interface on at least one of the circuit sides, the circuit side comprising a 5 to 10 microns thick conducting layer formed over one or more densely patterned metal interconnect layer for provision of a device power signal, a ground signal, an active device circuit signal and a frequency synchronization signal.   
     
     
         27 . The method of  claim 1 , wherein the plurality of dielectric structures includes a plurality of high-K dielectric structures. 
     
     
         28 . The method of  claim 1 , wherein the dielectric structures and conductive structures include a lateral interconnect network of metal lines within a device layer. 
     
     
         29 . The method of  claim 1 , further comprising:
 performing a layer transfer operation on the first substrate at room temperature.   
     
     
         30 . The method of  claim 29 , wherein the layer transfer operation is a room Temperature-Controlled Cleaving Process (rT-CCP™). 
     
     
         31 . The method of  claim 29 , further comprising bonding the cleave plane to a handle substrate before performing the layer transfer operation. 
     
     
         32 . A method comprising:
 implanting ions into a first substrate having dielectric structures and conductive structures when the first substrate is 250 degrees Celsius or less, the ions traveling through the plurality of conductive structures and the plurality of dielectric structures to define a cleave plane in the first substrate; and   subjecting a portion of the cleave plane to energy sufficient to remove an upper portion of the first substrate that includes the plurality of conductive structures and the plurality of dielectric structures from a lower bulk substrate material.   
     
     
         33 . The method of  claim 32 , wherein the first substrate is 150 degrees Celsius or less when the ions are implanted. 
     
     
         34 . A method comprising:
 implanting ions into a first semiconductor substrate having dielectric structures and conductive structures including an interconnect network of metal lines within a single device layer and a plurality of transistors, the ions traveling through the plurality of conductive structures and the plurality of dielectric structures to define a cleave plane in the first substrate; and   forming a cleaved layer by subjecting a portion of the cleave plane to energy sufficient to remove an upper portion of the first substrate that includes the plurality of conductive structures and the plurality of dielectric structures from a lower bulk substrate material,   wherein the cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.