Selective per-cycle masking of scan chains for system level test

Abstract

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

We claim: 
     
         1 . A circuit, comprising:
 a memory;   a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator;   a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals;   a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and   one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals.   
     
     
         2 . The circuit of  claim 1 , further comprising one or more logic gates operable to receive one or more of the input values applied to the ring generator and to produce a signal for selectively controlling when the shadow register control signal is applied to the shadow register. 
     
     
         3 . The circuit of  claim 1 , further comprising one or more logic gates operable to receive one or more of the ring generator output signals and to produce a control signal for selectively controlling when the shadow register control signal is applied to the shadow register. 
     
     
         4 . The circuit of  claim 1 , wherein the shadow register control signal is generated by a gate that selectively gates a clock signal. 
     
     
         5 . The circuit of  claim 4 , wherein the ring generator is clocked by the clock signal. 
     
     
         6 . The circuit of  claim 1 , wherein the phase shifter is configured to sustain one or more of the phase shifter output signals for more than one clock cycle. 
     
     
         7 . The circuit of  claim 1 , wherein the ring generator and the shadow register are configurable to be operated independently of each other. 
     
     
         8 . The circuit of  claim 1 , further comprising an XOR tree configured to control loading of the ring generator and the shadow register based on one or more of the ring generator input values. 
     
     
         9 . The circuit of  claim 1 , further comprising an XOR tree configured to control loading of the shadow register based on one or more of the ring generator output values. 
     
     
         10 . One or more computer-readable storage media storing design data describing the circuit of  claim 1 . 
     
     
         11 . A method, comprising:
 receiving circuit design information representative of a circuit-under-test; and   generating selection logic for testing the circuit-under-test, the selection logic comprising the circuit of  claim 1 .   
     
     
         12 . The method of  claim 11 , further comprising manufacturing an integrated circuit for the circuit-under-test, the integrated circuit tested at least in part using the selection logic. 
     
     
         13 . The method of  claim 11 , further comprising testing the circuit-under-test using the generated selection logic. 
     
     
         14 . One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of  claim 11 . 
     
     
         15 . A method, comprising:
 generating mask data indicating patterns of unknown states for which to mask test responses received from scan cells in an integrated circuit;   storing the mask data in a memory of the integrated circuit;   providing a selector configured to mask test responses produced by the scan cells based on the stored mask data, thereby producing masked test responses; and   providing a test response compactor configured to receive the masked test responses.   
     
     
         16 . The method of  claim 15 , wherein the generating mask data comprises mapping a pattern of the received test responses to one or more fault propagation sites designated among the scan cells. 
     
     
         17 . The method of  claim 15 , wherein the generating the mask data comprises selecting one or more of the scan cells based on the number of times an unknown state reaches the scan cells, the number of times faults are observed at the scan cells, or the number of times an unknown state reaches the scan cells and the number of times faults are observed at the scan cells, through a series of the received test responses. 
     
     
         18 . An integrated circuit, comprising:
 a circuit-under-test comprising one or more scan cells;   a memory storing mask data, the mask data indicating one or more of the scan cells to mask in scan cell test responses by masking patterns of unknown states in the test responses;   a selector configured to mask the received test responses responsive to the mask data, producing masked test responses; and   a compactor operable to receive the masked test responses.   
     
     
         19 . The circuit of  claim 18 , wherein the stored mask data is generated based at least in part based on rankings of the scan cells, the rankings based at least in part on an X-histogram and a D-histogram, the X-histogram indicating the number of times an unknown state reaches a given location at one or more of the scan cells throughout a series of the test responses, the D-histogram based at least in part on the number of faults observed at one or more of the scan cells throughout a series of the test responses. 
     
     
         20 . The circuit of  claim 18 , further comprising a group of circular mask registers coupled between the memory and the selector.