Three dimensional integrated circuit

Abstract

A device is formed by providing a first substrate, depositing a thickness of range compensating material on a first surface of the first substrate, implanting ions into the first substrate, the ions traveling through the range compensating material to define a cleave profile in the first substrate, the cleave profile including a contour that corresponds to the thickness of absorber material, removing the absorber material, and cleaving the first substrate at the cleave profile, thereby exposing the contour. A substrate with high thermal conductivity in which the contour defines a coolant channel effectively removes heat from a three-dimensional integrated circuit.

1 . A method of forming a device, the method comprising:
 providing a first substrate;   depositing a thickness of range compensating material on a first surface of the first substrate;   implanting ions into the first substrate, the ions traveling through the range compensating material to define a cleave profile in the first substrate, the cleave profile including at least one contour that corresponds to the thickness of absorber material;   removing the absorber material; and   cleaving the first substrate at the cleave profile, thereby exposing the at least one contour.   
     
     
         2 . The method of  claim 1 , wherein the at least one contour is a coolant channel. 
     
     
         3 . The method of  claim 2 , further comprising:
 after cleaving the first substrate, coating exposed surfaces of the coolant channel with a coating layer.   
     
     
         4 . The method of  claim 3 , wherein the coating material is a material that prevents a chemical reaction between a coolant fluid and the first substrate material. 
     
     
         5 . The method of  claim 3 , wherein the coating layer is a nitride material or an oxide material. 
     
     
         6 . The method of  claim 3 , wherein a thermal conductivity of the coating material is higher than a thermal conductivity of the first substrate. 
     
     
         7 . The method of  claim 1 , wherein the range compensating material is a photoresist material. 
     
     
         8 . The method of  claim 1 , wherein the first substrate has a thermal conductivity of at least 130 W/m-K at a temperature of 25 degrees Celsius. 
     
     
         9 . The method of  claim 8 , wherein the first substrate comprises carbon. 
     
     
         10 . The method of  claim 9 , wherein the first substrate is a diamond material or a graphite material. 
     
     
         11 . The method of  claim 1 , further comprising:
 bonding the cleaved surface of the first substrate to a second substrate having a circuit layer.   
     
     
         12 . The method of  claim 11 , wherein the first substrate is bonded to the second substrate by an oxide layer deposited on a surface of the second substrate. 
     
     
         13 . The method of  claim 12 , further comprising:
 after removing the range compensating layer, depositing a bonding layer on the first surface of the first substrate; and   bonding a third substrate comprising a circuit layer to the bonding layer on the first surface of the first substrate.   
     
     
         14 . The method of  claim 13 , wherein the first, second and third substrates are wafer scale substrates. 
     
     
         15 . A method of forming a three-dimensional integrated circuit, the method comprising:
 providing a first substrate;   depositing a thickness of range compensating material on a first surface of the first substrate;   implanting ions into the first substrate, the ions traveling through the range compensating material to define a cleave profile in the first substrate, the cleave profile including at least one contour that corresponds to the thickness of absorber material;   removing the absorber material;   cleaving the first substrate at the cleave profile, thereby exposing the at least one contour; and   bonding the first substrate to a second substrate that includes a circuit layer.   
     
     
         16 . The method of  claim 15 , wherein the at least one contour is a coolant channel. 
     
     
         17 . The method of  claim 16 , further comprising:
 depositing a coating that covers the at least one contour before bonding the first substrate to the second substrate.   
     
     
         18 . The method of  claim 17 , wherein a thermal conductivity of the coating layer is greater than a thermal conductivity of the first substrate. 
     
     
         19 . A method of forming a semiconductor device, the method comprising:
 providing a first substrate having dielectric and conductive structures;   depositing a thickness of range compensating material on a first surface of the first substrate;   implanting ions into the first substrate, the ions traveling through the dielectric and conductive structures and the range compensating material to define a cleave profile in the first substrate, the cleave profile including at least one contour that corresponds to the thickness of absorber material;   removing the absorber material; and   cleaving the first substrate at the cleave profile, thereby exposing the at least one contour.   
     
     
         20 . The method of  claim 19 , further comprising:
 after implanting the ions, exposing the first substrate to an atmosphere that includes a hydrogen gas and an inert gas at a temperature of from 350 degrees Celsius to 500 degrees Celsius for at least one half hour to repair damage to the dielectric and conductive structures.