Methods of tunnel oxide layer formation in 3d nand memory structures and associated devices

Abstract

3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

1 - 24 . (canceled) 
     
     
         25 . A 3D NAND memory structure comprising:
 a control gate and a floating gate disposed between a first insulating layer and a second insulating layer;   an interpoly dielectric (IPD) layer disposed between the control gate and the floating gate such that the IPD layer electrically isolates the control gate from the floating gate; and   a tunnel dielectric layer coupled to the floating gate opposite the control gate, wherein the floating gate is substantially free of curves at an interface with the tunnel dielectric layer.   
     
     
         26 . The memory structure of  claim 25 , wherein the floating gate is substantially flat at an interface with the tunnel dielectric layer. 
     
     
         27 . The memory structure of  claim 25 , wherein the floating gate is substantially flat along the entire interface with the tunnel dielectric layer. 
     
     
         28 . The memory structure of  claim 27 , wherein an intersection of an interface between the floating gate and the first insulating layer and an interface between the floating gate and the tunnel dielectric layer has an angle of from about 20 degrees to about 160 degrees. 
     
     
         29 . The memory structure of  claim 28 , wherein the angle is from about 45 degrees to 120 degrees. 
     
     
         30 . The memory structure of  claim 27 , wherein an intersection of an interface between the floating gate and the second insulating layer and an interface between the floating gate and the tunnel dielectric layer has an angle of from about 20 degrees to about 160 degrees. 
     
     
         31 . The memory structure of  claim 30 , wherein the angle is from about 45 degrees to 120 degrees. 
     
     
         32 . The memory structure of  claim 25 , wherein the tunnel dielectric layer has a thickness of from about 50 angstroms to about 80 angstroms. 
     
     
         33 . The memory structure of  claim 25 , wherein a portion of the floating gate along an interface with the tunnel dielectric layer is oxidized. 
     
     
         34 . The memory structure of  claim 33 , wherein the portion of the floating gate that is oxidized is about 10 angstroms or less beyond the tunnel dielectric layer interface. 
     
     
         35 . The memory structure of  claim 25 , wherein the floating gate has a size that is substantially the same as a size prior to creation of the tunnel dielectric layer. 
     
     
         36 . The memory structure of  claim 25 , wherein the tunnel dielectric layer is substantially free of dopant contamination from the floating gate. 
     
     
         37 . The memory structure of  claim 25 , wherein the floating gate has a substantially uniform dopant distribution. 
     
     
         38 . The memory structure of  claim 25 , wherein the floating gate has a shape that is substantially the same as a shape prior to creation of the tunnel dielectric layer. 
     
     
         39 . The memory structure of  claim 25 , wherein the floating gate has a height at an interface with the tunnel dielectric layer that is substantially the same as a height at an interface with the IPD layer. 
     
     
         40 . A method of forming a tunnel dielectric layer in a 3D NAND memory structure comprising:
 creating a layer of material on an exposed surface of a floating gate in a cell stack substrate, wherein said material either operates as the tunnel dielectric layer without further treatment, or operates as the tunnel dielectric layer after further treatment of the material.   
     
     
         41 . The method of  claim 40 , wherein the material is sufficient to operate as a tunnel dielectric layer without additional treatment. 
     
     
         42 . The method of  claim 40 , wherein the material created is a material that operates as a tunnel dielectric layer only after further treatment. 
     
     
         43 . The method of  claim 42 , wherein the further treatment comprises:
 oxidizing a portion of the material in the layer;   removing the oxidized portion of the material in the layer; and   oxidizing the remaining material in the layer.   
     
     
         44 . The method of  claim 40 , wherein the layer of material created is a member selected from the group consisting of: undoped polysilicon, polysilicon, or silicon nitride. 
     
     
         45 . The method of  claim 44 , wherein the material is undoped polysilicon. 
     
     
         46 . The method of  claim 40 , wherein the layer is a continuous layer extending from a top of the cell stack substrate to a bottom of the cell stack substrate. 
     
     
         47 . The method of  claim 40 , wherein the tunnel dielectric layer remains substantially free of dopant contamination from the floating gate. 
     
     
         48 . The method of  claim 40 , wherein the floating gate maintains a substantially uniform dopant distribution after formation of the tunnel dielectric layer.