Method of manufacturing chip package structure with conductive pillar

Abstract

A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

What is claimed is: 
     
         1 . A manufacturing method of a chip package structure, comprising:
 disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface;   forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface;   forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars;   forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars;   disposing a second semiconductor component within the perimeter of the first active surface, wherein the first encapsulant encapsulates the second semiconductor component, and the second semiconductor component is configured to be electrically connected to the first redistribution layer; and   removing the first carrier.   
     
     
         2 . The manufacturing method of the chip package structure as claimed in  claim 1 , wherein the second semiconductor component is disposed on the first active surface before the first encapsulant is formed, and the first encapsulant further encapsulates the second semiconductor component. 
     
     
         3 . The manufacturing method of the chip package structure as claimed in claim  2 , further comprising:
 forming a plurality of second conductive pillars on the second semiconductor component before the first encapsulant is formed, wherein each of the second conductive pillars is a solid cylinder, and the first encapsulant encapsulates the second conductive pillars and exposes an upper surface of each of the second conductive pillars, such that the second conductive pillars are electrically connected to the first redistribution layer.   
     
     
         4 . The manufacturing method of the chip package structure as claimed in  claim 2 , further comprising:
 forming a plurality of second conductive pillars on the second semiconductor component before the first encapsulant is formed, wherein each of the second conductive pillars is a solid cylinder, the second conductive pillars are encapsulated by the first encapsulant and connect between the first active surface and the second semiconductor component, such that the second semiconductor component is electrically connected to the first semiconductor component through the second conductive pillars.   
     
     
         5 . The manufacturing method of the chip package structure as claimed in  claim 1 , further comprising:
 forming a plurality of solder balls on the first redistribution layer, wherein the solder balls are electrically connected to the first redistribution layer.   
     
     
         6 . The manufacturing method of the chip package structure as claimed in  claim 3 , further comprising:
 disposing a third semiconductor component on the first redistribution layer;   forming a plurality of third conductive pillars on the third semiconductor component, wherein each of the third conductive pillars is a solid cylinder and electrically connected to the third semiconductor component;   forming a plurality of through pillars on the first redistribution layer, wherein each of the through pillars is a solid cylinder; and   forming a second encapsulant to encapsulate the third semiconductor component, the third conductive pillars and the through pillars, wherein the second encapsulant exposes an upper surface of each of the third conductive pillars and an upper surface of each of the through pillars.   
     
     
         7 . The manufacturing method of the chip package structure as claimed in  claim 6 , further comprising:
 disposing a fourth semiconductor component on the third semiconductor component;   forming a plurality of fourth conductive pillars on the fourth semiconductor component, wherein each of the fourth conductive pillars is a solid cylinder and electrically connected to the fourth semiconductor component, the second encapsulant encapsulates the fourth semiconductor component and the fourth conductive pillars and exposes an upper surface of each of the fourth conductive pillars; and   forming a second redistribution layer on the second encapsulant, wherein the second redistribution layer is electrically connected to the third conductive pillars, the through pillars and the fourth conductive pillars.   
     
     
         8 . The manufacturing method of the chip package structure as claimed in  claim 7 , further comprising:
 forming a plurality of solder balls on the second redistribution layer, wherein the solder balls are electrically connected to the second redistribution layer.   
     
     
         9 . The manufacturing method of the chip package structure as claimed in  claim 1 , further comprising:
 forming a plurality of first solder balls on the first redistribution layer, wherein the first solder balls are electrically connected to the first redistribution layer.   
     
     
         10 . The manufacturing method of the chip package structure as claimed in  claim 9 , further comprising:
 disposing a sub chip package on the first solder balls, wherein the sub chip package is electrically connected to the first solder balls, wherein the method of forming the sub chip package comprises:
 disposing the second semiconductor component on a second carrier, wherein the second semiconductor component comprises a second active surface and a plurality of second pads disposed on the second active surface; 
 forming a plurality of second conductive pillars on the second pads, wherein each of the second conductive pillars is a solid cylinder; 
 forming a plurality of through pillars on the second carrier, wherein the through pillars surround the second semiconductor component; 
 forming a second encapsulant to encapsulate the second semiconductor component, the second conductive pillars and the through pillars, wherein the second encapsulant exposes an upper surface of each of the second conductive pillars and an upper surface of each of the through pillars; 
 forming a second redistribution layer on the second encapsulant, wherein the second redistribution layer is electrically connected to the second conductive pillars and the through pillars; 
 forming a plurality of second solder balls on the second redistribution layer; and 
 removing the second carrier. 
   
     
     
         11 . The manufacturing method of the chip package structure as claimed in  claim 1 , wherein the second semiconductor component is disposed on the first active surface of only one first semiconductor component. 
     
     
         12 . The manufacturing method of the chip package structure as claimed in  claim 11 , wherein the only one first semiconductor component has a surface area greater than a surface area of the second semiconductor component. 
     
     
         13 . The manufacturing method of the chip package structure as claimed in  claim 11 , wherein the second semiconductor component is disposed on the first active surface before the first encapsulant is formed. 
     
     
         14 . The manufacturing method of the chip package structure as claimed in  claim 13 , wherein the first encapsulant is formed to further encapsulate the second semiconductor component. 
     
     
         15 . The manufacturing method of the chip package structure as claimed in  claim 1 , wherein the first encapsulant is integrally formed and in contact with side surfaces of the plurality of first conductive pillars.