Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects

Abstract

A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.

1 . A semiconductor device comprising:
 a substrate comprising a top surface and a bottom surface;   a semiconductor die bonded to the top surface of the substrate;   a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate;   a first conductive bump on the bottom surface of the substrate;   a second mold material encapsulating at least a portion of the first conductive bump and at least a portion of the bottom surface of the substrate; and   a second conductive bump arranged on the first conductive bump.   
     
     
         2 - 20 . (canceled) 
     
     
         21 . The semiconductor device of  claim 1 , wherein:
 a bottom of the first conductive bump is exposed through an opening in the second mold material, and   the second conductive bump is arranged on the bottom of the first conductive bump.   
     
     
         22 . The semiconductor device of  claim 1 , wherein:
 the first conductive bump comprises a first pillar and/or a first conductive ball, and   the second conductive bump comprises a second pillar and/or a second conductive ball.   
     
     
         23 . The semiconductor device of  claim 22 , wherein a first maximum width of the second conductive bump is greater than a second maximum width of the opening in the second mold material. 
     
     
         24 . The semiconductor device of  claim 22 , wherein the first conductive bump comprises the first conductive ball, the first conductive ball comprising solder. 
     
     
         25 . The semiconductor device of  claim 1 , wherein a bottom surface of the second mold material is substantially coplanar with a bottom of the first conductive bump. 
     
     
         26 . The semiconductor device of  claim 1 , wherein the second conductive bump is merged with the first conductive bump by a reflow process. 
     
     
         27 . The semiconductor device of  claim 1 , wherein the second mold material laterally surrounds an entirety of the first conductive bump. 
     
     
         28 . A semiconductor device comprising:
 a substrate comprising a top surface and a bottom surface;   a semiconductor die bonded to the top surface of the substrate;   a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate;   a first conductive bump having a top surface on the bottom surface of the substrate;   a second mold material on the bottom surface of the substrate and surrounding a side surface of the first conductive bump, the bottom of the first conductive bump exposed through an opening in the second mold material; and   a second conductive bump arranged on the bottom of the first conductive bump.   
     
     
         29 . The semiconductor device of  claim 28 , wherein:
 the first conductive bump comprises a first pillar and/or a first conductive ball, and   the second conductive bump comprises a second pillar and/or a second conductive ball.   
     
     
         30 . The semiconductor device of  claim 29 , wherein at least one of the first conductive bump or second conductive bump comprises copper. 
     
     
         31 . The semiconductor device of  claim 28 , wherein:
 a first maximum width of the second conductive bump is greater than a second maximum width of the opening in the second mold material, and   a third maximum width of the first conductive bump is greater than the second maximum width of the opening in the second mold material.   
     
     
         32 . The semiconductor device of  claim 28 , wherein the second mold material comprises a cavity in which the first conductive bump is positioned, and wherein a first maximum width of the cavity is greater than a second maximum width of the opening in the second mold material. 
     
     
         33 . The semiconductor device of  claim 28 , wherein a side surface of the second conductive bump extends laterally beyond a perimeter of the opening in the second mold material. 
     
     
         34 . The semiconductor device of  claim 28 , wherein:
 the second mold material comprises a cavity in which the first conductive bump is positioned, and   the cavity comprises an arcuate sidewall in a vertical cross-section view.   
     
     
         35 . A method of manufacture comprising:
 providing a structure comprising:
 a substrate comprising a top surface and a bottom surface; 
 a semiconductor die bonded to the top surface of the substrate; and 
 a first mold material that encapsulates the semiconductor die and at least a portion of the top surface of the substrate; 
   attaching a first conductive bump on the bottom surface of the substrate;   applying a second mold material to encapsulate at least a portion of the first conductive bump and at least a portion of the bottom surface of the substrate; and   attaching a second conductive bump on the first conductive bump.   
     
     
         36 . The method of  claim 35 , wherein the attaching the second conductive bump on the first conductive bump is performed using a reflow process. 
     
     
         37 . The method of  claim 35 , wherein:
 a bottom of the first conductive bump is exposed through the second mold material, and   the second conductive bump is attached on the bottom of the first conductive bump.   
     
     
         38 . The method of  claim 35 , further comprising planarizing a bottom surface of the second mold material and a bottom of the first conductive bump. 
     
     
         39 . The method of  claim 35 , wherein:
 the first conductive bump comprises a first conductive ball, and   the second conductive bump comprises a second conductive ball.