Semiconductor packages and methods of packaging semiconductor devices

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate;   an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;   a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer, wherein the conductive studs are disposed in the die region and the non-die region of the package substrate;   conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;   a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads;   a cap disposed over the package substrate to encapsulate the die, wherein a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed.   
     
     
         2 . The semiconductor package of  claim 1  comprising wherein the conductive traces are coupled to and contacts a top surface of the conductive studs. 
     
     
         3 . The semiconductor package of  claim 1  wherein a bottom of the cap contacts the conductive traces and the top surface of the insulating layer. 
     
     
         4 . The semiconductor package of  claim 1  wherein a bottom surface of the conductive studs partially covers and completely contacts a top surface of the via contacts. 
     
     
         5 . The semiconductor package of  claim 4  wherein a width of the conductive studs is smaller than a width of the via contacts. 
     
     
         6 . The semiconductor package of  claim 4  wherein the insulating layer partially covers the top surface of the via contacts. 
     
     
         7 . The semiconductor package of  claim 1  wherein a top surface of the conductive studs is coplanar with the top surface of the insulating layer. 
     
     
         8 . The semiconductor package of  claim 1  wherein the conductive studs are defined by a multi-layered stack of different conductive materials. 
     
     
         9 . The semiconductor package of  claim 1  wherein the via contacts are disposed in the die region and the non-die region of the package substrate, and a side surface of via contacts disposed at a periphery of the non-die region of the package substrate is exposed. 
     
     
         10 . A semiconductor package comprising:
 a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate, wherein the via contacts are disposed in the die region and the non-die region of the package substrate;   an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;   a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer;   conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;   a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads;   a cap disposed over the package substrate to encapsulate the die, wherein side surfaces of via contacts disposed at a periphery of the non-die region of the package substrate is exposed.   
     
     
         11 . The semiconductor package of  claim 10  wherein a top surface of the via contacts is coplanar to a top surface of the base substrate. 
     
     
         12 . The semiconductor package of  claim 11  wherein the top surface of the insulating layer is coplanar to a top surface of the conductive studs. 
     
     
         13 . The semiconductor package of  claim 10  wherein the conductive studs are disposed in the die region and the non-die region of the package substrate, and a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed. 
     
     
         14 . A semiconductor package comprising:
 a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate, and wherein the via contact comprises a width defined by circumference of the via contact;   an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;   a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer, wherein the conductive studs are disposed in the die region and the non-die region of the package substrate, wherein a width of the conductive stud which is defined by circumference of the conductive stud is smaller than the width of the via contacts;   conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;   a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads; and   a cap disposed over the package substrate to encapsulate the die.   
     
     
         15 . The semiconductor package of  claim 14  wherein a top surface of the conductive studs is coplanar with the top surface of the insulating layer. 
     
     
         16 . The semiconductor package of  claim 14  wherein the conductive studs are defined by a multi-layered stack of different conductive materials. 
     
     
         17 . The semiconductor package of  claim 14  wherein a top surface of the via contacts is coplanar to a top surface of the base substrate. 
     
     
         18 . The semiconductor package of  claim 16  wherein the conductive studs comprises a first conductive layer and a second conductive layer, the first conductive layer comprising a different conductive material to the second conductive layer. 
     
     
         19 . The semiconductor package of  claim 14  wherein the conductive studs are disposed in the die region and the non-die region of the package substrate, and a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed. 
     
     
         20 . The semiconductor package of  claim 14  wherein a bottom surface of the conductive studs partially covers and completely contacts a top surface of the via contacts.