Barrier layer removal method and semiconductor structure forming method

Abstract

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

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         24 . A barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal gas phase etching, wherein a chemical gas for thermal gas phase etching is one or more selected from a group consisting of XeF 2 , XeF 4 , and XeF 6 . 
     
     
         25 . The method as claimed in  claim 24 , wherein the temperature of thermal gas phase etching the barrier layer including Ru is 0° C. to 400° C. 
     
     
         26 . The method as claimed in  claim 25 , wherein the temperature of thermal gas phase etching the barrier layer including Ru is 100° C. to 350° C. 
     
     
         27 . The method as claimed in  claim 25 , wherein the temperature of thermal gas phase etching the barrier layer including Ru is 50° C. to 120° C. 
     
     
         28 . The method as claimed in  claim 24 , wherein the pressure of thermal gas phase etching the barrier layer including Ru is 10 to 20 Torr. 
     
     
         29 . The method as claimed in  claim 24 , wherein the flow rate of chemical gas is 0 to 50 sccm. 
     
     
         30 . The method as claimed in  claim 24 , wherein the temperature of thermal gas phase etching the barrier layer including Co is 120° C. to 600° C. 
     
     
         31 . The method as claimed in  claim 30 , wherein the temperature of thermal gas phase etching the barrier layer including Co is 200° C. to 400° C. 
     
     
         32 . The method as claimed in  claim 24 , wherein before the barrier layer is removed by thermal gas phase etching, a substrate surface may be treated by solution containing HF or gas phase treatment containing HF vapor. 
     
     
         33 . The method as claimed in  claim 24 , wherein the barrier layer includes another layer of which material is titanium, titanium nitride, tantalum or tantalum nitride. 
     
     
         34 . A semiconductor structure forming method, comprising:
 providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas;   removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas, wherein the metal surface in the recessed area is flush with the top surface of the dielectric layer;   removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal gas phase etching, wherein a chemical gas for thermal gas phase etching is one or more selected from a group consisting of XeF 2 , XeF 4 , and XeF 6 .   
     
     
         35 . The method as claimed in  claim 34 , wherein the barrier layer includes another layer of which material is titanium, titanium nitride, tantalum or tantalum nitride. 
     
     
         36 . The method as claimed in  claim 35 , wherein the metal layer formed on the non-recessed areas and the metal in the recessed area is removed by CMP or electropolishing, or the combination of CMP and electropolishing. 
     
     
         37 . The method as claimed in  claim 34 , further comprising treating the surface of the substrate by solution containing HF or gas phase treatment containing HF vapor before removing the barrier layer. 
     
     
         38 . A semiconductor structure forming method, comprising:
 providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas;   removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas, wherein the metal surface in the recessed area is below the top surface of the dielectric layer;   removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal gas phase etching, wherein a chemical gas for thermal gas phase etching is one or more selected from a group consisting of XeF 2 , XeF 4 , and XeF 6 .   
     
     
         39 . The method as claimed in  claim 38 , further comprising a step of selectively plating a cap layer on the metal surface in the recessed area. 
     
     
         40 . The method as claimed in  claim 39 , wherein the step of selectively plating a cap layer on the metal surface in the recessed area is carried out after the step of removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal gas phase etching. 
     
     
         41 . The method as claimed in  claim 38 , further comprising treating the surface of the substrate by solution containing HF or gas phase treatment containing HF vapor before removing the barrier layer. 
     
     
         42 . The method as claimed in  claim 38 , wherein the barrier layer includes another layer of which material is titanium, titanium nitride, tantalum or tantalum nitride. 
     
     
         43 . The method as claimed in  claim 38 , wherein the metal layer formed on the non-recessed areas and the metal in the recessed area is removed by CMP or electropolishing, or the combination of CMP and electropolishing.