Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an isolation insulating layer disposed over a substrate;   a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction;   a gate structure disposed over parts of the first and second fin structures, the gate structure extending in a second direction crossing the first direction;   a source/drain structure; and   a dielectric layer disposed on an upper surface of the isolation insulating layer, wherein:   the first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer,   the source/drain structure is formed over the recessed first and second fin structures, and   a void is formed between the source/drain structure and the dielectric layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the dielectric layer is formed of silicon nitride. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the dielectric layer has a sleeve shape. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the source/drain structure includes an epitaxial semiconductor layer and a part of the epitaxial semiconductor layer is disposed in the sleeve shape. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the dielectric layer is flat. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 an interlayer dielectric layer disposed over the first gate structure and the source/drain structure;   a silicide layer formed on the source/drain structure; and   a contact plug formed in the interlayer dielectric layer and connected to the silicide layer.   
     
     
         7 . The semiconductor device of  claim 6 , further comprising an etch stop layer disposed between the silicide layer and the interlayer dielectric layer. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a height of the void from an upper surface of the dielectric layer is in a range from 15 nm to 25 nm. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the dielectric layer is in contact with the first and second fin structures. 
     
     
         10 . A semiconductor device comprising:
 an isolation insulating layer disposed over a substrate;   a first fin structure, a second fin structure and a third fin structure, which are disposed over the substrate, the first, second and third fin structures extending in a first direction;   a source/drain structure disposed over source/drain regions of the first, second and third fin structures, the source/drain regions of the first, second and third fin structures being recessed   a first dielectric layer disposed on an upper surface of the isolation insulating layer between the first fin structure and the second fin structure;   a second dielectric layer disposed on the upper surface of the isolation insulating layer between the second fin structure and the third fin structure;   a first void is formed between the source/drain structure and the first dielectric layer; and   a second void is formed between the source/drain structure and the second dielectric layer.   
     
     
         11 . The semiconductor device of  claim 9 , wherein the first and second dielectric layers are formed of silicon nitride. 
     
     
         12 . The semiconductor device of  claim 9 , wherein each of the first and second dielectric layers has a sleeve shape. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the source/drain structure includes an epitaxial semiconductor layer and a part of the epitaxial semiconductor layer is disposed in the sleeve shape. 
     
     
         14 . The semiconductor device of  claim 9 , wherein each of the first and second dielectric layers is flat. 
     
     
         15 . The semiconductor device of  claim 9 , further comprising a gate structure disposed over channel regions of the first, second and third fin structures. 
     
     
         16 . The semiconductor device of  claim 15 , further comprising:
 an interlayer dielectric layer disposed over the gate structure and the source/drain structure;   a silicide layer formed on the source/drain structure; and   a contact plug formed in the interlayer dielectric layer and connected to the silicide layer.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising a etch stop layer disposed between the silicide layer and the interlayer dielectric layer. 
     
     
         18 . The semiconductor device of  claim 10 , wherein a height of each of the first and second voids from an upper surface of the dielectric layer is in a range from 15 nm to 25 nm. 
     
     
         19 . The semiconductor device of  claim 10 , wherein the first dielectric layer is in contact with the first and second fin structures, and the second dielectric layer is in contact with the second and third fin structures. 
     
     
         20 . A semiconductor device comprising:
 an isolation insulating layer disposed over a substrate;   a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction;   a source/drain structure; and   a dielectric layer disposed on an upper surface of the isolation insulating layer, wherein:   parts of the first and second fin structures are recessed,   the source/drain structure is formed over the recessed parts of the first and second fin structures, and   a void is formed between the source/drain structure and the dielectric layer.