Low dielectric constant oxide and low resistance op stack for 3d nand application

Abstract

Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1−x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

What is claimed is: 
     
         1 . A method of manufacturing a memory device stack, comprising:
 positioning a substrate in a PECVD chamber;   depositing a silicon oxide layer over the substrate; and   introducing a silicon precursor and germane to the PECVD chamber to form a silicon-germanium film over the silicon oxide layer.   
     
     
         2 . The method of  claim 1 , wherein the depositing a silicon oxide layer over the substrate comprises:
 introducing octamethylcyclotetrasiloxane precursor to the PECVD chamber to deposit the silicon oxide layer.   
     
     
         3 . The method of  claim 1 , further comprising:
 annealing the silicon-germanium film to form a polysilicon layer comprising silicon and germanium over the silicon oxide layer.   
     
     
         4 . The method of  claim 1 , further comprising:
 generating a plasma in the PECVD chamber.   
     
     
         5 . The method of  claim 4 , wherein introducing the silicon precursor and germane to the PECVD chamber occurs before generating the plasma in the PECVD chamber. 
     
     
         6 . The method of  claim 3 , further comprising:
 plasma treating an interface between the silicon oxide layer and the polysilicon layer, wherein the plasma treatment comprises introducing ammonia and/or nitrogen to the PECVD chamber.   
     
     
         7 . The method of  claim 1 , wherein the silicon-germanium film is doped. 
     
     
         8 . The method of  claim 7 , where in the silicon-germanium film is doped with phosphine. 
     
     
         9 . A memory device, comprising:
 a substrate;   a silicon oxide layer disposed over the substrate, the silicon oxide layer having a dielectric constant between about 2.5 and about 3.2; and   a polysilicon layer disposed over the silicon oxide layer.   
     
     
         10 . The memory device of  claim 9 , wherein the dielectric constant of the silicon oxide layer is between about 2.8 and about 3.0. 
     
     
         11 . The memory device of  claim 9 , wherein the silicon oxide layer is deposited on and in contact with the substrate and wherein the polysilicon layer is deposited on and in contact with the silicon oxide layer. 
     
     
         12 . The memory device of  claim 9 , wherein the polysilicon layer is an n-type polysilicon layer, and wherein the n-type polysilicon layer has a resistivity of less than about 0.5×10 −3  ohm*cm. 
     
     
         13 . The memory device of  claim 9 , wherein the polysilicon layer is a p-type polysilicon layer, and wherein the p-type polysilicon layer has a resistivity of less than about 1.5×10 −3  ohm*cm. 
     
     
         14 . A method of manufacturing a memory device stack, comprising:
 positioning a substrate in a PECVD chamber;   depositing a silicon oxide layer over the substrate by introducing octamethylcyclotetrasiloxane precursor to the PECVD chamber, the silicon oxide layer having a dielectric constant between about 2.5 and about 3.2; and   introducing a silicon precursor and germane to the PECVD chamber to form a silicon-germanium film over the silicon oxide layer.   
     
     
         15 . The method of  claim 14 , further comprising:
 annealing the silicon-germanium film to form a polysilicon layer comprising silicon and germanium over the silicon oxide layer.   
     
     
         16 . The method of  claim 15 , further comprising:
 plasma treating an interface between the silicon oxide layer and the polysilicon layer, wherein the plasma treatment comprises introducing ammonia and/or nitrogen to the PECVD chamber.   
     
     
         17 . The method of  claim 14 , wherein the silicon-germanium film is doped. 
     
     
         18 . The method of  claim 17 , where in the silicon-germanium film is doped with phosphine. 
     
     
         19 . The method of  claim 14 , further comprising:
 generating a plasma in the PECVD chamber.   
     
     
         20 . The method of  claim 19 , wherein introducing the silicon precursor and germane to the PECVD chamber occurs before generating the plasma in the PECVD chamber.