Transistors with dual gate conductors, and associated methods

Abstract

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

What is claimed is: 
     
         1 . A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor, comprising:
 a silicon semiconductor structure; and   a vertical gate, including:
 a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, 
 a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and 
 a gate dielectric layer separating each of first the gate conductor and the second gate conductor from the silicon semiconductor structure. 
   
     
     
         2 . The LDMOS transistor of  claim 1 , wherein the first separation dielectric layer separates the first gate conductor from the second gate conductor in each of the thickness direction and a lateral direction, the lateral direction being orthogonal to the thickness direction. 
     
     
         3 . The LDMOS transistor of  claim 1 , wherein the first gate conductor is adjacent to a drain region of the LDMOS transistor in a lateral direction, the lateral direction being orthogonal to the thickness direction. 
     
     
         4 . The LDMOS transistor of  claim 3 , wherein the second gate conductor is adjacent to a source region of the LDMOS transistor in the lateral direction. 
     
     
         5 . The LDMOS transistor of  claim 1 , wherein:
 the silicon semiconductor structure includes:
 a base layer, 
 an n-type layer disposed over the base layer in a thickness direction, 
 a p-body region disposed in the n-type layer, 
 a source n+ region disposed in the p-body region, and 
 a drain n+ region disposed in the n-type layer; and 
   each of the first gate conductor and the second gate conductor is disposed between the source n+ region and the drain n+ region in a lateral direction orthogonal to the thickness direction.   
     
     
         6 . The LDMOS transistor of  claim 5 , further comprising:
 a source electrode electrically coupled to the source n+ region;   a drain electrode electrically coupled to the drain n+ region; and   a first gate electrode electrically coupled to the first gate conductor.   
     
     
         7 . The LDMOS transistor of  claim 6 , wherein the first gate electrode is additionally electrically coupled to the second gate conductor. 
     
     
         8 . The LDMOS transistor of  claim 6 , further comprising a second gate electrode electrically coupled to the second gate conductor. 
     
     
         9 . The LDMOS transistor of  claim 5 , further comprising a p-type reduced surface field effect (RESURF) layer disposed below the vertical gate in the thickness direction. 
     
     
         10 . The LDMOS transistor of  claim 1 , wherein the vertical gate further includes:
 a third gate conductor; and   a second separation dielectric layer separating the first gate conductor from the third gate conductor within the vertical gate.   
     
     
         11 . The LDMOS transistor of  claim 10 , wherein the second separation dielectric layer separates the first gate conductor from the third gate conductor in the thickness direction. 
     
     
         12 . The LDMOS transistor of  claim 10 , wherein the gate dielectric layer further separates the third gate conductor from the silicon semiconductor structure. 
     
     
         13 . The LDMOS transistor of  claim 10 , wherein:
 the first gate conductor is adjacent to a drain region of the LDMOS transistor in a lateral direction, the lateral direction being orthogonal to the thickness direction;   the second gate conductor is adjacent to a source region of the LDMOS transistor in the lateral direction; and   the third gate conductor is adjacent to a well region of the LDMOS transistor in the thickness direction.   
     
     
         14 . The LDMOS transistor of  claim 1 , wherein the gate dielectric layer includes a least three dielectric sections, each of the at least three dielectric sections separating the gate conductor from the silicon semiconductor structure by a respective separation distance, each of the respective separation distances being different from each other of the respective separation distances. 
     
     
         15 . An integrated circuit, comprising:
 the LDMOS transistor of  claim 1 ; and   a trench capacitor, including:
 a first capacitor conductor and a second capacitor conductor each extending from the first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in the thickness direction, and 
 a capacitor dielectric layer separating each of the first capacitor conductor and the second capacitor conductor from the silicon semiconductor structure. 
   
     
     
         16 . The integrated circuit of  claim 15 , further comprising a spacer dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate. 
     
     
         17 . The integrated circuit of  claim 15 , further comprising driver circuitry configured to drive the vertical gate of the LDMOS transistor, wherein:
 the driver circuitry is powered from a first power rail; and   the trench capacitor is electrically coupled across the first power rail.   
     
     
         18 . A method for forming a vertical gate of a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor, the method comprising the steps of:
 forming a trench dielectric layer in a trench of a silicon semiconductor structure;   filling the trench with a first conductive material;   removing a portion of the first conductive material from the trench;   after the step of removing the portion of the first conductive material from the trench, removing a portion of the trench dielectric layer in a first area of the trench;   disposing a first separation dielectric layer on the first conductive material in the trench;   forming a source portion of a gate dielectric layer in the first area of the trench; and   filling a portion of the trench not containing the first conductive material with a second conductive material.   
     
     
         19 . The method of  claim 18 , further comprising, before filing the trench with the first conductive material:
 filing the trench with a third conductive material;   removing a portion of the third conductive material from the trench; and   after the step of removing the portion of the third conductive material from the trench, disposing a second separation dielectric layer on the third conductive material.   
     
     
         20 . A method for forming an integrated circuit, comprising the steps of:
 forming a vertical gate of a LDMOS transistor according to the method of  claim 18 ; and   executing at least the following steps to form a trench capacitor:
 forming a capacitor dielectric layer in a second trench of the silicon semiconductor structure; 
 filling the second trench with a third conductive material; 
 removing a portion of the third conductive material from the second trench; and 
 filling a portion of the second trench not containing the third conductive material with a fourth conductive material.