Offset interposers for large-bottom packages and large-die package-on-package structures

Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

What is claimed is: 
     
         1 . A package-on-package (POP) structure comprising:
 a processor device mechanically and electrically coupled to a substrate;   a first ball grid array (BGA) electrically and mechanically coupled to the processor;   an interposer electrically and mechanically coupled to the processor device, wherein the interposer comprises:   a first side comprising a first array of pads, wherein a first pad and a second pad of the first array are adjacent to each other on the first side, and wherein the first pad is coupled to a first electrical interconnect structure of the first BGA, and wherein the second land side pad is coupled to a second electrical interconnect structure of the first BGA, and wherein the first array of pads comprises a first perimeter dimension; and   a second side comprising a second array of pads, wherein a first pad and a second pad of the second array are adjacent to each other on the second side, and wherein the first pad on the second side is electrically coupled with the first pad on the first side through the interposer, and wherein the second pad on the second side and the second pad on the first side are electrically coupled to each other through the interposer, and wherein the second array of pads comprises a second perimeter dimension, wherein the first perimeter dimension is larger than the second perimeter dimension;   a second BGA comprising a plurality of electrical interconnect structures, wherein the first pad of the second array of pads is coupled with a first electrical interconnect structure of the second BGA, and wherein the second pad of the second array of pads is coupled with a second electrical interconnect structure of the second BGA; and   a memory device mechanically and electrically coupled to the second BGA.