Fin structures of finfet devices

Abstract

A FinFET device is provided, which includes a semiconductor substrate, a fin structure and a dielectric material. The fin structure is extending from the semiconductor substrate, the fin structure having an upper fin section, a middle fin section and a lower fin section. The dielectric material is over the semiconductor substrate embedding a first portion of the lower fin section. The dielectric material forms shallow trench isolation regions of the FinFET device.

1 . A FinFET device comprising:
 a semiconductor substrate; and   a fin structure extending from the semiconductor substrate, wherein the fin structure has an upper fin portion and a lower fin portion, the lower fin portion is embedded in a dielectric material over the semiconductor substrate and the upper fin portion vertically extends from the lower fin portion above the dielectric material and comprises curved concave side surfaces spaced apart from the dielectric material and   wherein the dielectric material forms shallow trench isolation regions of the FinFET device.   
     
     
         2 . The FinFET device of  claim 1 , wherein the upper fin portion has a first width where the curved concave side surfaces are laterally closest and a second width at an intersection with an upper surface of the dielectric material and the first width is narrower than the second width. 
     
     
         3 . The FinFET device of  claim 2 , wherein the first width is at least 7% narrower than the second width. 
     
     
         4 . (canceled) 
     
     
         5 . The FinFET device of  claim 1 , wherein the upper fin portion is an active region for the FinFET device. 
     
     
         6 . (canceled) 
     
     
         7 . The FinFET device of  claim 2 , wherein the first width is at least 0.5 nm narrower than the second width. 
     
     
         8 . The FinFET device of  claim 2 , wherein the first width ranges from 4 nm to 30 nm. 
     
     
         9 . The FinFET device  claim 1 , wherein the curved concave side surfaces have a height ranging from 5 nm to 30 nm. 
     
     
         10 . (canceled) 
     
     
         11 . The FinFET device of  claim 1 , wherein the lower fin portion has a height ranging from 50 nm to 100 nm. 
     
     
         12 . The FinFET device of  claim 1 , wherein the curved concave side surfaces are 5 nm to 30 nm above the dielectric material. 
     
     
         13 . A method of fabricating a FinFET device comprising:
 providing a semiconductor substrate;   forming an upper fin portion from the semiconductor substrate, wherein the upper fin portion comprises curved concave side surfaces;   forming a lower fin portion from the semiconductor substrate, wherein the upper and the lower fin portions together form a fin structure of the FinFET device; and   forming shallow trench isolation regions adjacent to and covering the lower fin portion, wherein the curved concave side surfaces are spaced apart therefrom.   
     
     
         14 . The method of  claim 13 , wherein forming the curved concave side surfaces comprises an isotropic etching process. 
     
     
         15 . The method of  claim 13 , wherein forming the lower fin portion comprises an anisotropic etching process. 
     
     
         16 . The method of  claim 13 , wherein forming the shallow trench isolation regions further comprises:
 depositing a dielectric material over the semiconductor substrate and covering the fin structure; and   recessing the dielectric material to form the shallow trench isolation regions, exposing the upper fin portion.   
     
     
         17 . A method of fabricating a FinFET device comprising:
 providing a semiconductor substrate;   forming an upper fin portion from the semiconductor substrate, wherein the upper fin portion comprises curved concave side surfaces having a first width where the curved concave side surfaces are laterally closest;   forming a lower fin portion from the semiconductor substrate; and   depositing a dielectric material to form shallow trench isolation regions covering the lower fin portion, wherein the lower fin portion has a second width at an intersection with an upper surface of the dielectric material and the curved concave side surfaces are spaced apart from the dielectric material.   
     
     
         18 . The method of  claim 17 , wherein the second width is wider than the first width. 
     
     
         19 . The method of  claim 17 , wherein the curved concave side surfaces are formed by isotropically removing material from the semi conductor substrate. 
     
     
         20 . (canceled)