US2021151457A1PendingUtilityA1
Three-dimensional memory structure, three-dimensional memory device and electronic apparatus
Assignee: YANGTZE MEMORY TECH CO LTDPriority: Nov 23, 2017Filed: Jan 31, 2021Published: May 20, 2021
Est. expiryNov 23, 2037(~11.3 yrs left)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H01L 27/11582H01L 21/76224H01L 27/11575H01L 27/11529H01L 27/11556H01L 27/11548H01L 27/11573H10B 41/50H10B 41/27H10B 41/41H10B 43/40H10B 43/27H10B 43/50
60
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A 3D memory structure, a 3D memory device and an electronic apparatus are disclosed and include a substrate having a recess, a 3D memory component with a bottom disposed in the recess of the substrate, and a peripheral circuit disposed on the substrate outside the recess.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A 3D memory structure, comprising:
a substrate having a recess; a 3D memory component with a bottom disposed in the recess of the substrate; and a peripheral circuit disposed on the substrate outside the recess.
2 . The 3D memory structure of claim 1 , wherein a depth of the recess is greater than or equal to a thickness of the 3D memory component.
3 . The 3D memory structure of claim 1 , wherein the 3D memory component comprises:
an alternating conductor/dielectric stack, comprising a plurality of dielectric layers and a plurality of conductor layers, and each dielectric layer and each conductor layer are stacked alternately; and a plurality of NAND strings through the alternating conductor/dielectric stack.
4 . The 3D memory structure of claim 3 , further comprising a first insulation layer disposed on the alternating conductor/dielectric stack, wherein the NAND strings extend through the first insulation layer.
5 . The 3D memory structure of claim 1 , further comprising a second insulation layer and a metal connection layer, wherein the second insulation layer is disposed on the peripheral circuit and the 3D memory component, the metal connection layer is disposed on the second insulation layer, and the peripheral circuit is electrically connected to the 3D memory component through the metal connection layer.
6 . The 3D memory structure of claim 5 , further comprising an interconnection layer disposed between the second insulation layer and the metal connection layer.
7 . A 3D memory device, comprising the 3D memory structure of claim 1 .
8 . An electronic apparatus, comprising the 3D memory device of claim 7 .Join the waitlist — get patent alerts
Track US2021151457A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.