Memory Arrays Comprising Operative Channel-Material Strings And Dummy Pillars

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

1 . A memory array comprising strings of memory cells, comprising:
 laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;   first dummy pillars in the laterally-spaced memory blocks extending through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend; and   second dummy pillars laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the laterally-spaced memory blocks, the second dummy pillars extending through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks.   
     
     
         2 . The memory array of  claim 1  wherein the first dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend. 
     
     
         3 . The memory array of  claim 1  wherein the second dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend. 
     
     
         4 . The memory array of  claim 1  wherein the first and second dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend. 
     
     
         5 . The memory array of  claim 1  wherein the first and second dummy pillars extend through the same insulative and conductive tiers. 
     
     
         6 . The memory array of  claim 1  wherein the first and second dummy pillars have the same height. 
     
     
         7 . The memory array of  claim 6  wherein the operative channel-material strings have common height relative one another and that is said same height. 
     
     
         8 . The memory array of  claim 1  wherein the first and second dummy pillars individually comprise peripherally-surrounding insulative material elevationally there-along. 
     
     
         9 . The memory array of  claim 8  wherein the first and second dummy pillars individually at least predominately comprise the insulative material. 
     
     
         10 . The memory array of  claim 9  wherein the first and second dummy pillars individually at least consist essentially of the insulative material. 
     
     
         11 . The memory array of  claim 10  wherein the first and second dummy pillars individually consists of the insulative material. 
     
     
         12 . The memory array of  claim 1  wherein the first and second dummy pillars extend vertically or within 10° of vertical. 
     
     
         13 . The memory array of  claim 1  wherein the immediately-adjacent memory blocks have a maximum lateral-separation distance of 120 to 220 nanometers in an uppermost of the insulative tiers. 
     
     
         14 . The memory array of  claim 13  wherein said maximum lateral-separation distance is no more than 150 nanometers. 
     
     
         15 . The memory array of  claim 1  wherein the first dummy pillars individually have a minimum horizontal width of 50 to 100 nanometers in an uppermost of the insulative tiers. 
     
     
         16 . The memory array of  claim 1  wherein the vertical stack comprises:
 a lower stack comprising vertically-alternating lower insulative tiers and lower conductive tiers, the lower stack comprising lower-laterally-spaced memory blocks; 
 an upper stack directly above the lower stack, the upper stack comprising vertically-alternating upper insulative tiers and upper conductive tiers above the lower stack, the upper stack comprising upper-laterally-spaced memory blocks that are directly above the lower-laterally-spaced memory-blocks; 
 the operative channel-material strings of the memory cells extending through the upper insulative tiers, the upper conductive tiers, the lower insulative tiers, and the lower conductive tiers; 
 the first dummy pillars extending through at least a majority of the upper insulative tiers, the upper conductive tiers, the lower insulative tiers, and the lower conductive tiers through which the operative channel-material strings extend; and 
 the second dummy pillars being laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the upper and lower memory blocks, the second dummy pillars extending through at least a majority of the upper insulative tiers, the upper conductive tiers, the lower insulative tiers, and the lower conductive tiers through which the operative channel-material strings extend. 
 
     
     
         17 . The memory array of  claim 16  wherein the upper and lower stacks are immediately-vertically-adjacent one another. 
     
     
         18 . A memory array comprising strings of memory cells, comprising:
 laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, immediately-adjacent of the laterally-spaced memory blocks having a maximum lateral-separation distance of 120 to 220 nanometers in an uppermost of the insulative tiers; and   dummy pillars in the laterally-spaced memory blocks extending through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend, the dummy pillars individually having a minimum horizontal width of 50 to 100 nanometers in the uppermost insulative tier.   
     
     
         19 . The memory array of  claim 18  comprising dummy pillars laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks, the dummy pillars that are laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks extending through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend. 
     
     
         20 . The memory array of  claim 18  wherein said maximum lateral-separation distance is no more than 150 nanometers. 
     
     
         21 - 40 . (canceled)