Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages

Abstract

A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

What is claimed is: 
     
         1 . An electronic package, comprising:
 a substrate having a side with a lowermost layer of conductive vias; and   an electronic component embedded in the substrate, the electronic component having an uppermost layer of conductive landing pad features with a layer of conductive vias disposed thereon, wherein one of the conductive landing pad features is coupled directly to a conductive via of the electronic component which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.   
     
     
         2 . The electronic package of  claim 1 , wherein the substrate comprises a layer encapsulating the conductive via of the substrate but not encapsulating the conductive via of the electronic component. 
     
     
         3 . The electronic package of  claim 2 , wherein the layer is a dielectric layer. 
     
     
         4 . The electronic package of  claim 1 , further comprising:
 a film disposed adjacent to the conductive via of the electronic component.   
     
     
         5 . The electronic package of  claim 1 , wherein the conductive via of the electronic component and the conductive via of the substrate are self-aligned. 
     
     
         6 . The electronic package of  claim 1 , wherein the conductive via of the substrate, the conductive via of the electronic component, and the conductive landing pad feature comprise copper. 
     
     
         7 . An electronic package, comprising:
 a substrate, comprising:
 a side with a lowermost layer of conductive vias; and 
 a layer encapsulating the layer of conductive vias; and 
 an electronic component embedded in the substrate, the electronic component comprising:
 an uppermost layer of conductive landing pad features, wherein at least one of the conductive landing pad features is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate; and 
 a conformal layer disposed on and covering at least a portion of the uppermost layer of conductive landing pad features, wherein the layer of the substrate is disposed directly on the conformal layer. 
 
   
     
     
         8 . The electronic package of  claim 7 , wherein the conductive via and the conductive landing pad feature comprise copper. 
     
     
         9 . An electronic package, comprising:
 a substrate, comprising:
 a side with a lowermost layer of conductive routing; and 
 a next lowermost layer of conductive routing disposed directly on the lowermost layer of conductive routing; and 
 an electronic component embedded in the substrate, the electronic component having an uppermost layer of conductive landing pad features, wherein one of the conductive landing pad features is coupled directly to the lowermost layer of conductive routing of the substrate. 
   
     
     
         10 . The electronic package of  claim 9 , wherein the substrate further comprises a film encapsulating the lowermost layer of conductive routing. 
     
     
         11 . The electronic package of  claim 10 , wherein the electronic component further comprises a conformal layer disposed on and covering at least a portion of the uppermost layer of conductive landing pad features, wherein film is disposed directly on the conformal layer. 
     
     
         12 . The electronic package of  claim 9 , wherein the next lowermost layer of conductive routing is a layer of conductive traces. 
     
     
         13 . The electronic package of  claim 12 , wherein the lowermost layer of conductive routing is a layer of conductive vias. 
     
     
         14 . The electronic package of  claim 12 , wherein the lowermost layer of conductive routing is a layer of conductive traces. 
     
     
         15 . The electronic package of  claim 9 , wherein the lowermost layer of conductive routing is, from a top-down perspective, confined to the size of the electronic component. 
     
     
         16 . The electronic package of  claim 9 , wherein the conductive landing pad feature of the electronic component and the lowermost layer of conductive routing of the substrate comprise copper.