Packaging substrate and semiconductor apparatus comprising same

Abstract

The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

What is claimed is: 
     
         1 . A semiconductor apparatus comprising:
 a semiconductor element unit where one or more semiconductor elements are disposed; a packaging substrate electrically connected to the semiconductor element; and a motherboard electrically connected to the packaging substrate, transmitting electrical signals of the semiconductor element and external, and connecting each other;   wherein a packaging substrate comprises a core layer, and an upper layer disposed on the core layer,   wherein the core layer comprises a glass substrate and a core via,   the glass substrate is with a first surface and a second surface facing each other,   the core via penetrating through the glass substrate in a thickness direction is disposed in a plural number,   the core layer comprises a core distribution layer disposed on a surface of the glass substrate or the core via,   the core distribution layer comprises an electrically conductive layer at least a part of which electrically connect an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via, and   the upper layer is disposed on the first surface and comprises an electrically conductive layer which electrically connect the core distribution layer and semiconductor element unit of external;   wherein the core via comprises a first surface opening part diameter, a second surface opening part diameter, and a minimum inner diameter,   wherein the first surface opening part diameter is a diameter at an opening part in contact with the first surface,   the second surface opening part diameter is a diameter at an opening part in contact with the second surface, and   the minimum inner diameter is a diameter at the narrowest area disposed between the first surface opening part and the second surface opening part, and   wherein at a position of the minimum inner diameter, a thickness of the electrically conductive layer is 90% or more, when a distance from an inner diameter surface of the core via to a surface of an electrically conductive layer of the core via is 100% as total.   
     
     
         2 . The semiconductor apparatus of  claim 1 ,
 wherein at an opening part where a larger one between the first surface opening part diameter and the second surface opening part diameter is disposed, a thickness of the electrically conductive layer is 90% or more, when a distance from an inner diameter surface of the core via to a surface of an electrically conductive layer of the core via distribution pattern is 100% as total.   
     
     
         3 . The semiconductor apparatus of  claim 1 , further comprising:
 an upper insulating layer and an upper distribution pattern,   wherein the upper insulating layer is an insulating layer disposed on the first surface,   the upper distribution pattern is an electrically conductive layer at least a part of which is electrically connected to the core distribution layer,   the upper distribution pattern is built in the upper insulating layer,   the upper distribution pattern is at least partially comprising a fine pattern, and   the fine pattern has a width and an interval of less than 4 μm, respectively.   
     
     
         4 . The semiconductor apparatus of  claim 1 ,
 wherein the packaging substrate has a resistance value of about 27.5×10 −6 Ω or less, based on a cut one of the packaging substrate into 100 μm×100 μm as an upper surface size.   
     
     
         5 . A packaging substrate comprising:
 a core layer, and an upper layer disposed on the core layer,   wherein the core layer comprises a glass substrate and a core via,   the glass substrate is with a first surface and a second surface facing each other,   the core via penetrating through the glass substrate in a thickness direction is disposed in a plural number,   the core layer comprises a core distribution layer disposed on a surface of the glass substrate or the core via,   the core distribution layer comprises an electrically conductive layer at least a part of which electrically connect an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via, and   the upper layer is disposed on the first surface and comprises an electrically conductive layer which electrically connect the core distribution layer and semiconductor element unit of external;   wherein the core via comprises a first surface opening part diameter, a second surface opening part diameter, and a minimum inner diameter,   wherein the first surface opening part diameter is a diameter at an opening part in contact with the first surface,   the second surface opening part diameter is a diameter at an opening part in contact with the second surface, and   the minimum inner diameter is a diameter at the narrowest area disposed between the first surface opening part and the second surface opening part, and   wherein at a position of the minimum inner diameter, a thickness of the electrically conductive layer is 90% or more, when a distance from an inner diameter surface of the core via to a surface of an electrically conductive layer of the core via is 100% as total.   
     
     
         6 . A semiconductor apparatus comprising:
 a semiconductor element unit where one or more semiconductor elements are disposed; a packaging substrate electrically connected to the semiconductor element; and a motherboard electrically connected to the packaging substrate, transmitting electrical signals of the semiconductor element and external, and connecting each other;   wherein a packaging substrate comprises a core layer, and an upper layer disposed on the core layer,   wherein the core layer comprises a glass substrate and a core via,   the glass substrate is with a first surface and a second surface facing each other,   the core via penetrating through the glass substrate in a thickness direction is disposed in a plural number,   the core layer comprises a core distribution layer disposed on a surface of the glass substrate or the core via,   the core distribution layer comprises an electrically conductive layer at least a part of which electrically connect an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via, and   the upper layer is disposed on the first surface and comprises an electrically conductive layer which electrically connect the core distribution layer and semiconductor element unit of external;   wherein the core distribution layer comprises a first surface core pattern, a second surface core pattern, and a core via pattern,   wherein the first surface core pattern is an electrically conductive layer disposed on at least a part of the first surface,   the second surface core pattern is an electrically conductive layer disposed on at least a part of the second surface, and   the core via pattern is an electrically conductive layer electrically connecting the first surface core pattern and the second surface core pattern through the core via, and   wherein the core via pattern has an average distance of 1 μm or less, between one surface of the core via pattern close to an inner diameter surface of the core via; and the inner diameter surface of the core via.   
     
     
         7 . The semiconductor apparatus of  claim 6 ,
 wherein the core via has a first surface opening part diameter, a second surface opening part diameter and a minimum inner diameter,   wherein the first surface opening part diameter is a diameter at an opening part in contact with the first surface,   the second surface opening part diameter is a diameter at an opening part in contact with the second surface, and   the minimum inner diameter is a diameter at the narrowest area disposed between the first surface opening part and the second surface opening part, and   wherein at a position of the minimum inner diameter, a thickness of the electrically conductive layer is 90% or more, when a distance from an inner diameter surface of the core via to a surface of an electrically conductive layer of the core via is 100% as total.   
     
     
         8 . The semiconductor apparatus of  claim 7 ,
 wherein the packaging substrate has a resistance value of about 27.5×10 −6 Ω or less, based on a cut one of the packaging substrate into 100 μm×100 μm as an upper surface size.   
     
     
         9 . The semiconductor apparatus of  claim 6 , further comprising:
 an upper insulating layer and an upper distribution pattern,   wherein the upper insulating layer is an insulating layer disposed on the first surface,   the upper distribution pattern is an electrically conductive layer at least a part of which is electrically connected to the core distribution layer,   the upper distribution pattern is built in the upper insulating layer,   the upper distribution pattern is at least partially including a fine pattern, and   the fine pattern has a width and an interval of less than 4 μm, respectively.   
     
     
         10 . A packaging substrate comprising:
 a core layer, and an upper layer disposed on the core layer,   wherein the core layer comprises a glass substrate and a core via,   the glass substrate is with a first surface and a second surface facing each other,   the core via penetrating through the glass substrate in a thickness direction is disposed in a plural number,   the core layer comprises a core distribution layer disposed on a surface of the glass substrate or the core via,   the core distribution layer comprises an electrically conductive layer at least a part of which electrically connect an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via, and   the upper layer is disposed on the first surface and comprises an electrically conductive layer which electrically connect the core distribution layer and semiconductor element unit of external;   wherein the core distribution layer comprises a first surface core pattern, a second surface core pattern, and a core via pattern,   wherein the first surface core pattern is an electrically conductive layer disposed on at least a part of the first surface,   the second surface core pattern is an electrically conductive layer disposed on at least a part of the second surface, and   the core via pattern is an electrically conductive layer electrically connecting the first surface core pattern and the second surface core pattern through the core via, and   wherein the core via pattern has an average distance of 1 μm or less, between one surface of the core via pattern close to an inner diameter surface of the core via; and the inner diameter surface of the core via.