Mos capacitor and fabrication method thereof

Abstract

A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

1 . A metal-oxide-semiconductor (MOS) capacitor, comprising:
 a substrate comprising a capacitor forming region thereon;   a P-type ion well in the substrate;   an N +  counter doping region in the P-type ion well within the capacitor forming region;   a capacitor dielectric layer on the P-type ion well within the capacitor forming region;   a gate electrode on the capacitor dielectric layer;   an N +  source doping region on a first side of the gate electrode within the capacitor forming region; and   an N +  drain doping region on a second side of the gate electrode within the capacitor forming region wherein the N +  counter doping region has a junction depth that is deeper than that of the N +  source doping region or the N +  drain doping region, and wherein the N +  counter doping region is in direct contact with the N +  source doping region and the N +  drain doping region, and wherein the N +  counter doping region is completely overlapped with the gate electrode.   
     
     
         2 - 3 . (canceled) 
     
     
         4 . The MOS capacitor according to  claim 1 , wherein the counter doping region is located between the source doping region and the drain doping region and is situated directly under the gate electrode. 
     
     
         5 . The MOS capacitor according to  claim 1 , wherein the counter doping region is merged with the source doping region and the drain doping region. 
     
     
         6 . The MOS capacitor according to  claim 5 , wherein the counter doping region, the source doping region, and the drain doping region are electrically connected to a low voltage, and wherein the gate electrode is electrically connected to a high voltage, thereby constituting a capacitor across the capacitor dielectric layer. 
     
     
         7 . (canceled) 
     
     
         8 . The MOS capacitor according to  claim 1 , wherein the substrate comprises a silicon substrate. 
     
     
         9 . The MOS capacitor according to  claim 1 , wherein the capacitor dielectric layer is a core oxide layer. 
     
     
         10 . The MOS capacitor according to  claim 9 , wherein the core oxide layer has a thickness less than 58 angstroms. 
     
     
         11 . A method of forming a metal-oxide-semiconductor (MOS) capacitor, comprising:
 providing a substrate comprising a capacitor forming region thereon;   forming an ion well having a first conductivity type in the substrate;   forming a counter doping region having a second conductivity type in the ion well within the capacitor forming region;   forming a capacitor dielectric layer on the ion well within the capacitor forming region;   forming a gate electrode on the capacitor dielectric layer;   forming a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region; and   forming a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.   
     
     
         12 . The method of forming a MOS capacitor according to  claim 11 , wherein the first conductivity type is P type and the second conductivity type is N type. 
     
     
         13 . The method of forming a MOS capacitor according to  claim 11 , wherein said forming a counter doping region having a second conductivity type in the ion well within the capacitor forming region comprises:
 implanting dopants having the second conductivity type into the ion well with an energy of about 15-25 KeV and a dosage of about 1E 15-5E15 atoms/cm 2 ; and   subjecting the counter doping region and the ion well to a rapid thermal anneal (RTP) process at a temperature of about 950-1060 degrees Celsius.   
     
     
         14 . The method of forming a MOS capacitor according to  claim 11 , wherein the counter doping region is located between the source doping region and the drain doping region and is situated directly under the gate electrode. 
     
     
         15 . The method of forming a MOS capacitor according to  claim 11 , wherein the counter doping region is merged with the source doping region and the drain doping region. 
     
     
         16 . The method of forming a MOS capacitor according to  claim 15 , wherein the counter doping region, the source doping region, and the drain doping region are electrically connected to a low voltage, and wherein the gate electrode is electrically connected to a high voltage, thereby constituting a capacitor across the capacitor dielectric layer. 
     
     
         17 . The method of forming a MOS capacitor according to  claim 16 , wherein the low voltage is a ground voltage and the high voltage is between −2.8V-2.8V. 
     
     
         18 . The method of forming a MOS capacitor according to  claim 11 , wherein the substrate comprises a silicon substrate. 
     
     
         19 . The method of forming a MOS capacitor according to  claim 11 , wherein the capacitor dielectric layer is a core oxide layer. 
     
     
         20 . The method of forming a MOS capacitor according to  claim 19 , wherein the core oxide layer has a thickness less than 58 angstroms.