US2022230800A1PendingUtilityA1

Techniques for an inductor at a first level interface

Assignee: INTEL CORPPriority: Jun 19, 2018Filed: Apr 5, 2022Published: Jul 21, 2022
Est. expiryJun 19, 2038(~11.9 yrs left)· nominal 20-yr term from priority
H10W 20/497H10W 90/22H10W 72/01H10W 74/15H10W 72/9445H10W 72/922H10W 72/29H10W 70/654H10W 70/65H10W 90/00H10W 72/073H10W 72/07232H10W 72/072H10W 72/241H10W 72/354H10W 90/724H10W 90/722H10W 72/07254H10W 72/253H10W 72/225H10W 72/252H10W 72/242H10W 90/734H10W 44/501H10W 90/401H10W 70/611H10W 70/635H10D 84/038H10D 1/20H01F 2017/0066H01F 2027/2814H01F 17/0013H01F 41/041H01F 27/24H01F 27/2804H01L 28/10H01L 23/5227H01L 21/822H04B 5/0075H04B 5/24
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Claims

Abstract

Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor die having a plurality of external terminations;   a substrate coupled to the semiconductor die with a number of solder interconnects;   an inductor winding comprising at least some of the plurality of external terminations, the number of solder interconnects, and a plurality of traces in the substrate; and   a layer of magnetic material disposed in a space between the semiconductor die and the substrate, the layer of magnetic material located within the number of solder interconnects between the semiconductor die and the substrate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the layer of magnetic material is attached to the semiconductor die. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the layer of magnetic material is attached to the substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the number of solder interconnects includes a number of solder balls. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the number of solder interconnects are arranged in two parallel rows. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the traces in the substrate are on a surface of the substrate adjacent to the semiconductor die. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the traces in the substrate are on a surface of the substrate facing away from the semiconductor die. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the magnetic material includes an insulating magnetic material. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the magnetic material includes an FeXN, where X includes one or more metal element. 
     
     
         10 . A semiconductor device, comprising:
 a semiconductor die having a plurality of external terminations;   an interposer coupled to the semiconductor die with a first number of solder interconnects;   a substrate coupled to the interposer with a second number of solder interconnects;   an inductor winding comprising at least some of the plurality of external terminations, the number of first solder interconnects, the number of second solder interconnects, and a plurality of traces in the substrate; and   a layer of magnetic material disposed in a space between the semiconductor die and the interposer, the layer of magnetic material located within the number of first number of solder interconnects between the semiconductor die and the interposer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the interposer includes a silicon interposer. 
     
     
         12 . The semiconductor device of  claim 10 , further including a second layer of magnetic material disposed in a space between the interposer and the substrate, the second layer of magnetic material located within the number of second number of solder interconnects between the interposer and the substrate. 
     
     
         13 . The semiconductor device of  claim 10 , wherein the layer of magnetic material includes an insulating magnetic material. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the layer of magnetic material includes an FeXN, where X includes one or more metal element. 
     
     
         15 . The semiconductor device of  claim 12 , wherein the second layer of magnetic material includes an insulating magnetic material. 
     
     
         16 . The semiconductor device of  claim 12 , wherein the second layer of magnetic material includes an FeXN, where X includes one or more metal element.

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