Methods Of Forming Metal Gate Spacer

Abstract

A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

What is claimed is: 
     
         1 . A method, comprising:
 providing dummy gate structures disposed over an active region and over an isolation region adjacent to the active region, a first gate spacer disposed along sidewalls of the dummy gate structures over the active region, and a second gate spacer disposed along sidewalls of the dummy gate structures over the isolation region;   removing top portions of the second gate spacer, but not the first gate spacer;   forming a first dielectric layer over the first gate spacer and remaining portions of the second gate spacer;   after forming the first dielectric layer, replacing the dummy gate structures with metal gate structures;   after replacing the dummy gate structures, removing the first gate spacer; and   forming a second dielectric layer over top surfaces of the metal gate structures and the first dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the first and the second gate spacers include the same composition. 
     
     
         3 . The method of  claim 1 , wherein removing the top portions of the second gate spacer includes:
 forming a patterned mask over the active region, thereby exposing the isolation region; and   selectively etching the top portions of the second gate spacer relative to the dummy gate structures over the isolation region.   
     
     
         4 . The method of  claim 1 , wherein removing the top portions of the second gate spacer includes removing no more than about 70% of a height of the second gate spacer. 
     
     
         5 . The method of  claim 1 , wherein removing the first gate spacer includes forming an air gap disposed between sidewalls of the metal gate structures and the first dielectric layer over the active region, and wherein the forming of the second dielectric layer includes sealing the air gap. 
     
     
         6 . The method of  claim 1 , wherein removing the first gate spacer includes selectively etching the first gate spacer relative to the first dielectric layer. 
     
     
         7 . The method of  claim 1 , wherein the active region includes source/drain features disposed therein, the method further comprising, after the forming of the second dielectric layer, forming source/drain contacts over the source/drain features, the source/drain contacts being disposed between the metal gate structures. 
     
     
         8 . A method, comprising:
 providing a workpiece comprising first dummy gate structures disposed directly on an isolation feature, first gate spacer layers extending along sidewall surfaces of the first dummy gate structures, and second gate spacer layers extending along sidewall surfaces of the first gate spacer layers;   selectively recessing the second gate spacer layers without substantially etching the first gate spacer layers;   conformally depositing a first dielectric layer over the workpiece;   depositing a second dielectric layer over the first dielectric layer; and   replacing the first dummy gate structures with metal gate stacks.   
     
     
         9 . The method of  claim 8 , wherein the first gate spacer layers comprise a lower portion in direct contact with the recessed second gate spacer layers and an upper portion in direct contact with the first dielectric layer. 
     
     
         10 . The method of  claim 8 , wherein the first gate spacer layers comprise a greater amount of carbon than the recessed second gate spacer layers. 
     
     
         11 . The method of  claim 8 , wherein the workpiece further comprises:
 a fin-shaped active region adjacent the isolation feature;   second dummy gate structures over channel regions of the fin-shaped active region;   source/drain features coupled to the channel regions;   third gate spacer layers extending along sidewall surfaces of the second dummy gate structures; and   fourth gate spacer layers extending along sidewall surfaces of the third gate spacer layers;   wherein heights of the second dummy gate structures are less than heights of the first dummy gate structures.   
     
     
         12 . The method of  claim 11 , further comprising:
 replacing the second dummy gate structures with metal gate stacks; and   selectively removing the fourth gate spacer layers to form air gaps exposing sidewall surfaces of the third gate spacer layers.   
     
     
         13 . The method of  claim 11 , wherein top surfaces of the recessed second gate spacer layers are above a top surface of the fin-shaped active region. 
     
     
         14 . A method, comprising:
 providing a workpiece comprising first dummy gate structures engaging an active region and second dummy gate structures directly over an isolation feature adjacent to the active region, a first gate spacer layer disposed along sidewalls of the first dummy gate structures, and a second gate spacer layer disposed along sidewalls of the second dummy gate structures;   performing an etching process to selectively recess the second gate spacer layer;   selectively removing the first dummy gate structures and the second dummy gate structures to form gate trenches;   forming metal gate stacks in the gate trenches; and   after the forming of the metal gate stacks, selectively removing the first gate spacer layer to form air gaps over the active region.   
     
     
         15 . The method of  claim 14 , wherein the selectively recessing of the second gate spacer layer comprises:
 forming a patterned mask over the workpiece, the patterned mask covering the first gate spacer layer and exposing the second gate spacer layer; and   selectively removing top portions of the second gate spacer layer relative to the second dummy gate structures.   
     
     
         16 . The method of  claim 14 , after the performing of the etching process, a top surface of a remaining portion of the second gate spacer layer is above a top surface of the active region. 
     
     
         17 . The method of  claim 14 , further comprising:
 before the selectively removing of the first dummy gate structures and the second dummy gate structures, depositing a first dielectric layer over the workpiece, wherein the first dielectric layer covers the first gate spacer layer and a remaining portion of the second gate spacer layer;   depositing a second dielectric layer over the first dielectric layer; and   performing a planarization process to the workpiece to expose a top surface of gate electrodes in the first and second dummy gate structures and expose the first gate spacer layer without exposing the remaining portion of the second gate spacer layer.   
     
     
         18 . The method of  claim 14 , wherein a top surface of the isolation feature is below a top surface of the active region and comprises a concave surface. 
     
     
         19 . The method of  claim 14 , wherein heights of portions of the metal gate stacks over the isolation feature are greater than heights of portions of the metal gate stacks over the active region. 
     
     
         20 . The method of  claim 14 , wherein each of the first gate spacer layer and the second gate spacer layer comprises a multi-layer structure that includes a first layer and a second layer extending along a sidewall surface of the first layer, wherein the performing of the etching process selectively recesses the second layer of the second gate spacer layer without substantially etching the first layer of the second gate spacer layer.