Stacked architecture for three-dimensional nand

Abstract

Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.

1 - 20 . (canceled) 
     
     
         21 . A method for forming a device stack comprising a logic section, a first memory section comprising a set of landing pads, and a second memory section, the method comprising:
 removing a first sacrificial substrate from the first memory section, wherein the set of landing pads are adjacent to the first sacrificial substrate prior to removing the first sacrificial substrate from the first memory section;   subsequent to removing the first sacrificial substrate, adding a redistribution layer to the first memory section, wherein the redistribution layer is connected to the set of landing pads;   bonding the redistribution layer of the first memory section to the second memory section; and   bonding the logic section to the first memory section.   
     
     
         22 . The method of  claim 21 , wherein the second memory section is on a substrate. 
     
     
         23 . The method of  claim 21 , wherein the second memory section is on a second sacrificial substrate. 
     
     
         24 . The method of  claim 21 , wherein the logic section comprises a first set of bonding pads and the first memory section comprises a second set of bonding pads, and bonding the logic section to the first memory section comprises bonding the first set of bonding pads to the second set of bonding pads. 
     
     
         25 . The method of  claim 21 , wherein the redistribution layer comprises one or more dielectric layers. 
     
     
         26 . The method of  claim 21 , wherein bonding the redistribution layer of the first memory section to the second memory section comprises hybrid bonding. 
     
     
         27 . The method of  claim 21 , wherein a first side of the redistribution layer is connected to the set of landing pads and a second side of the redistribution layer opposite to the first side comprises a set of hybrid bonding pads. 
     
     
         28 . The method of  claim 21 , wherein each of the first and second memory sections comprises a memory pyramid. 
     
     
         29 . A method for forming a device stack comprising a logic section, a first memory section comprising a set of landing pads, and a second memory section, the method comprising:
 removing a first sacrificial substrate from the first memory section, wherein the set of landing pads are adjacent to the first sacrificial substrate prior to removing the first sacrificial substrate from the first memory section;   adding a redistribution layer to the first memory section, wherein the redistribution layer is connected to the set of landing pads;   bonding the redistribution layer of the first memory section to the second memory section; and   subsequent to bonding the redistribution layer of the first memory section to the second memory section, bonding the logic section to the first memory section.   
     
     
         30 . The method of  claim 29 , wherein the second memory section is on a substrate. 
     
     
         31 . The method of  claim 29 , wherein the second memory section is on a second sacrificial substrate. 
     
     
         32 . The method of  claim 29 , wherein bonding the logic section to the first memory section comprises hybrid bonding. 
     
     
         33 . The method of  claim 29 , wherein the logic section comprises a first set of bonding pads, the first memory section comprises a second set of bonding pads, and bonding the logic section to the first memory section comprises bonding the first set of bonding pads to the second set of bonding pads. 
     
     
         34 . The method of  claim 33 , wherein a first side of the redistribution layer is connected to the set of landing pads and a second side of the redistribution layer opposite to the first side comprises the second set of bonding pads. 
     
     
         35 . A method for forming a stack of memory sections on a first memory section on a substrate, the method comprising:
 forming a second memory section comprising a redistribution layer connected to a set of landing pads, wherein the redistribution layer comprises a first set of bonding pads, and wherein the redistribution layer is formed subsequent to removing a sacrificial substrate that is adjacent to the set of landing pads; and   bonding the redistribution layer to the first memory section.   
     
     
         36 . The method of  claim 35 , further comprising:
 bonding a logic section to a bonding surface of the second memory section.   
     
     
         37 . The method of  claim 36 , wherein:
 the logic section comprises a second set of bonding pads;   the bonding surface of the second memory section comprises a third set of bonding pads; and   bonding the logic section to the bonding surface of the second memory section comprises bonding the second set of bonding pads to the third set of bonding pads.   
     
     
         38 . The method of  claim 35 , wherein bonding the redistribution layer to the first memory section comprises hybrid bonding. 
     
     
         39 . The method of  claim 35 , wherein each of the first and second memory sections comprises a memory pyramid. 
     
     
         40 . The method of  claim 35 , wherein forming the stack of memory sections comprises forming a stacked memory device, the stacked memory device comprising a logic section bonded to the second memory section, and the method further comprises:
 bonding the logic section to the second memory section.   
     
     
         41 . The method of  claim 35 , wherein forming the stack of memory sections comprises forming a stacked memory device, the stacked memory device comprising a logic section bonded to a third memory section, the method further comprising:
 forming a third memory section on the second memory section; and   bonding the logic section to the third memory section.   
     
     
         42 . The method of  claim 35 , wherein forming the stack of memory sections comprises forming a stacked memory device, the stacked memory device comprising a third memory section bonded to the second memory section and a logic section bonded to a fourth memory section, and the method further comprises:
 bonding the logic section to the fourth memory section.   
     
     
         43 . A method for forming a memory device comprising a bonded stack of a bottommost memory section, one or more intermediate memory sections, and a topmost memory section, each of the one or more intermediate and topmost memory sections comprising a redistribution layer, the method comprising:
 bonding the topmost memory section to one of the intermediate memory sections; and   subsequent to bonding the topmost memory section to one of the intermediate memory sections, bonding a logic section to the topmost memory section.   
     
     
         44 . The method of  claim 43 , wherein bonding the logic section to the topmost memory section comprises bonding the logic section to the redistribution layer of the topmost memory section.