Chip arrangement, chip package, method of forming a chip arrangement, and method of forming a chip package

Abstract

A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.

What is claimed is: 
     
         1 . A chip arrangement, comprising:
 a chip comprising a first main surface, wherein the first main surface comprises an active area, a chip termination portion, and at least one contact pad;   a first dielectric layer at least partially covering the chip termination portion and the active area, and at least partially exposing the at least one contact pad; and   a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.   
     
     
         2 . The chip arrangement of  claim 1 ,
 wherein the first dielectric layer has a larger thickness than the second dielectric layer.   
     
     
         3 . The chip arrangement of  claim 1 ,
 wherein a material of the first dielectric layer is different from a material of the second dielectric layer.   
     
     
         4 . The chip arrangement of  claim 1 ,
 wherein the first dielectric layer includes or consists of at least one of a group of materials, the group comprising:
 an organic material; 
 an oxide; and 
 a nitride. 
   
     
     
         5 . The chip arrangement of  claim 1 ,
 wherein the second dielectric layer includes or consists of at least one of a group of materials, the group comprising:
 Al 2 O 3 ; 
 SiO 2 ; 
 HfO 2 ; 
 ZrO 2 ; 
 TiO 2 ; 
 Ta 2 O 5 ; 
 AlN; 
 BN; 
 TiN; 
 TaN; and 
 Si 3 N 4 . 
   
     
     
         6 . The chip arrangement of  claim 5 ,
 wherein the first dielectric layer includes or consists of an imide.   
     
     
         7 . The chip arrangement of  claim 1 ,
 wherein the chip comprises a second main surface opposite the first main surface, and side surfaces connecting the first main surface and the second main surface, and   wherein the second dielectric layer further at least partially covers the side surfaces.   
     
     
         8 . The chip arrangement of  claim 1 , further comprising:
 wherein a thickness of the second dielectric layer is in a range from about 2 nm to about 100 nm.   
     
     
         9 . The chip arrangement of  claim 1 , further comprising:
 a third dielectric layer at least partially covering the second dielectric layer.   
     
     
         10 . The chip arrangement of  claim 9 ,
 wherein the third dielectric layer includes or consists of at least one of a group of materials, the group comprising:
 Al 2 O 3 ; 
 SiO 2 ; 
 HfO 2 ; 
 ZrO 2 ; 
 TiO 2 ; 
 Ta 2 O 5 ; 
 AlN; 
 BN; 
 TiN; 
 TaN; 
 Si 3 N 4 ; and 
 an organic material. 
   
     
     
         11 . The chip arrangement of  claim 1 , further comprising:
 a metal contact structure, the metal contact structure electrically contacting the contact pad.   
     
     
         12 . The chip arrangement of  claim 11 ,
 wherein the second dielectric layer further at least partially covers the metal contact structure.   
     
     
         13 . The chip arrangement of  claim 1 , further comprising:
 a carrier;   wherein the chip is mounted on the carrier,   wherein the carrier comprises exposed metal; and   wherein the second dielectric layer further at least partially covers the exposed metal of the carrier.   
     
     
         14 . The chip arrangement of  claim 13 ,
 wherein the exposed metal is arranged on a side of the carrier to which the chip is mounted.   
     
     
         15 . A chip package, comprising:
 the chip arrangement of  claim 1 ; and   packaging material at least partially encapsulating the chip.   
     
     
         16 . The chip package of  claim 15 ,
 wherein the packaging material is in direct contact with the second dielectric layer.   
     
     
         17 . The chip package of  claim 15 ,
 wherein the chip arrangement comprises the third dielectric layer of  claim 9 , and   wherein the packaging material is in direct contact with the third dielectric layer.   
     
     
         18 . The chip package of  claim 15 ,
 wherein the chip arrangement comprises the carrier of  claim 14 , and   wherein the packaging material at least partially encapsulates the carrier.   
     
     
         19 . A method of forming a chip arrangement, the method comprising:
 forming a first dielectric layer at least partially covering a chip termination portion and an active area on a first main surface of a chip, and at least partially exposing at least one contact pad on the first main surface of the chip; and   forming a second dielectric layer over the first dielectric layer and over the at least one contact pad by atomic layer deposition.   
     
     
         20 . The method of  claim 19 ,
 wherein the first dielectric layer has a larger thickness than the second dielectric layer,   wherein a material of the first dielectric layer is different from a material of the second dielectric layer,   wherein the chip comprises a second main surface opposite the first main surface, and side surfaces connecting the first main surface and the second main surface,   wherein the second dielectric layer further at least partially covers the side surfaces, and   forming a third dielectric layer at least partially covering the second dielectric layer.