Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages

Abstract

A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

What is claimed is: 
     
         1 . An electronic package, comprising:
 a semiconductor die;   a conductive landing pad on the semiconductor die;   an insulating film over the semiconductor die, the insulating film having an opening over at least a portion of the conductive landing pad;   a conductive via on a first portion of the conductive landing pad, the conductive via in the opening of the insulating film, and the conductive via having an uppermost surface;   a dielectric layer on the insulating film, the dielectric layer on a second portion of the conductive landing pad, the dielectric layer in the opening of the insulating film, the dielectric layer laterally adjacent to and in contact with the conductive via, and the dielectric layer having an uppermost surface; and   a conductive line on the uppermost surface of the conductive via and on the uppermost surface of the dielectric layer.   
     
     
         2 . The electronic package of  claim 1 , wherein uppermost surface of the dielectric layer is co-planar with the uppermost surface of the conductive via. 
     
     
         3 . The electronic package of  claim 1 , wherein the conductive via and the conductive landing pad forma bumpless interface. 
     
     
         4 . The electronic package of  claim 1 , wherein the conductive via has tapered sidewalls. 
     
     
         5 . The electronic package of  claim 1 , wherein the insulating film is a passivating film. 
     
     
         6 . The electronic package of  claim 1 , wherein the insulating film is photo-sensitive. 
     
     
         7 . An electronic package, comprising:
 a semiconductor die;   a conductive landing pad on the semiconductor die, the conductive landing pad having a top surface having an inner region within a perimeter region;   an insulating film over the semiconductor die, the insulating film on the perimeter region of the top surface of the conductive landing pad but not on the inner region of the top surface of the conductive landing pad;   a conductive via on a first portion of the inner region of the top surface of the conductive landing pad, the conductive via having an uppermost surface;   a dielectric layer on the insulating film, the dielectric layer on a second portion of the inner region of the top surface of the conductive landing pad, the first portion of the inner region of the top surface of the conductive pad within the second portion of the inner region of the top surface of the conductive pad, the dielectric layer laterally adjacent to and in contact with the conductive via, and the dielectric layer having an uppermost surface; and   a conductive line on the uppermost surface of the conductive via and on the uppermost surface of the dielectric layer.   
     
     
         8 . The electronic package of  claim 7 , wherein uppermost surface of the dielectric layer is co-planar with the uppermost surface of the conductive via. 
     
     
         9 . The electronic package of  claim 7 , wherein the conductive via and the conductive landing pad forma bumpless interface. 
     
     
         10 . The electronic package of  claim 7 , wherein the conductive via has tapered sidewalls. 
     
     
         11 . The electronic package of  claim 7 , wherein the insulating film is a passivating film. 
     
     
         12 . The electronic package of  claim 7 , wherein the insulating film is photo-sensitive. 
     
     
         13 . A computer system, comprising:
 a system bus; and   an electronic package coupled to the system bus, the electronic package comprising:
 a semiconductor die; 
 a conductive landing pad on the semiconductor die; 
 an insulating film over the semiconductor die, the insulating film having an opening over at least a portion of the conductive landing pad; 
 a conductive via on a first portion of the conductive landing pad, the conductive via in the opening of the insulating film, and the conductive via having an uppermost surface; 
 a dielectric layer on the insulating film, the dielectric layer on a second portion of the conductive landing pad, the dielectric layer in the opening of the insulating film, the dielectric layer laterally adjacent to and in contact with the conductive via, and the dielectric layer having an uppermost surface; and 
 a conductive line on the uppermost surface of the conductive via and on the uppermost surface of the dielectric layer. 
   
     
     
         14 . The computer system of  claim 13 , further comprising:
 a voltage source coupled to the system bus.   
     
     
         15 . The computer system of  claim 13 , further comprising:
 a processor coupled to the system bus.   
     
     
         16 . The computer system of  claim 13 , further comprising:
 a memory coupled to the system bus.   
     
     
         17 . The computer system of  claim 13 , further comprising:
 a display coupled to the system bus.   
     
     
         18 . The computer system of  claim 13 , further comprising:
 a camera coupled to the system bus.   
     
     
         19 . The computer system of  claim 13 , further comprising:
 a digital sound recorder coupled to the system bus.   
     
     
         20 . The computer system of  claim 13 , further comprising:
 a voice recognition device coupled to the system bus.