Gate structure of semiconductor device and method of forming same

Abstract

A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

What is claimed is: 
     
         1 . A device comprising:
 a fin extending from a substrate;   an isolation structure over the substrate and adjacent the fin, wherein a top surface of the fin is above a top surface of the isolation structure;   a gate dielectric layer along the top surface and sidewalls of the fin and the top surface of the isolation structure, wherein a first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin; and   a gate electrode layer over the gate dielectric layer.   
     
     
         2 . The device of  claim 1 , wherein a ratio of the first thickness to the second thickness is greater than 1 and less than about 1.2. 
     
     
         3 . The device of  claim 1 , wherein the first thickness is in a range between 10 Å and 30 Å. 
     
     
         4 . The device of  claim 1 , further comprising an interfacial layer between the fin and the gate dielectric layer. 
     
     
         5 . The device of  claim 1 , wherein the gate dielectric layer comprises a first layer, the first layer comprising:
 a first conformal sublayer comprising a first material; and   a first non-conformal sublayer over the first conformal sublayer, the first non-conformal sublayer comprising a second material different from the first material.   
     
     
         6 . The device of  claim 5 , wherein a third thickness of the first non-conformal sublayer over a top surface of the fin is in a range between 2 Å and 10 Å, wherein a fourth thickness of the first non-conformal sublayer over a sidewall of the fin is in a range between 1 Å and 6 Å. 
     
     
         7 . The device of  claim 6 , wherein a ratio of the third thickness to the fourth thickness is in a range between 1.6 and 2.5. 
     
     
         8 . The device of  claim 6 , wherein a thickness of the first conformal sublayer is in a range between 5 Å and about 20 Å. 
     
     
         9 . The device of  claim 5 , wherein the gate dielectric layer further comprises one or more second layers over the first layer, wherein each of the one or more second layers comprise:
 a second conformal sublayer; and   a second non-conformal sublayer over the second conformal sublayer.   
     
     
         10 . A device comprising:
 a fin extending from a substrate;   an isolation structure over the substrate and adjacent the fin, wherein a top surface of the fin is above a top surface of the isolation structure;   an interfacial layer along the top surface and sidewalls of the fin;   a gate dielectric layer over the interfacial layer along the top surface and sidewalls of the fin, wherein the gate dielectric layer comprises one or more conformal sub-layers and one or more non-conformal sub-layers, wherein a first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin; and   a gate electrode layer over the gate dielectric layer.   
     
     
         11 . The device of  claim 10 , wherein the gate dielectric layer alternates between one of the one or more non-conformal sub-layers and one of the one or more non-conformal sub-layers. 
     
     
         12 . The device of  claim 10 , wherein a third thickness of a first conformal sub-layer of the one or more conformal sub-layers along the top surface of the fin is in a range between 2 Å and about 10 Å, wherein a fourth thickness of the first conformal sub-layer of the one or more conformal sub-layers along the sidewalls of the fin is in a range between 1 Å and about 6 Å. 
     
     
         13 . The device of  claim 12 , wherein a ratio of the third thickness to the fourth thickness is in a range between 1.6 and 2.5. 
     
     
         14 . The device of  claim 10 , wherein the one or more conformal sub-layers are a different material than the one or more non-conformal sub-layers. 
     
     
         15 . The device of  claim 10 , wherein a bottommost conformal layer is between a bottommost non-conformal layer and the interfacial layer. 
     
     
         16 . A device comprising:
 a fin extending from a substrate;   an isolation structure over the substrate and adjacent the fin, wherein a top surface of the fin is above a top surface of the isolation structure;   a gate dielectric layer along the top surface and sidewalls of the fin and the top surface of the isolation structure, wherein a first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin, wherein the gate dielectric layer comprises at least one conformal dielectric sub-layer and at least one non-conformal dielectric sub-layer; and   a gate electrode layer over the gate dielectric layer.   
     
     
         17 . The device of  claim 16 , wherein the gate dielectric layer comprises a plurality of pairs of the conformal dielectric sub-layer and the non-conformal dielectric sub-layer, wherein the conformal dielectric sub-layers and the non-conformal dielectric sub-layers are arranged in an alternating manner. 
     
     
         18 . The device of  claim 16 , wherein a ratio of the first thickness to the second thickness is greater than 1 and less than about 1.2. 
     
     
         19 . The device of  claim 16 , wherein the first thickness is in a range between 10 Å and 30 Å. 
     
     
         20 . The device of  claim 16 , wherein the at least one conformal dielectric sub-layer is a different material than the at least one non-conformal dielectric sub-layer.